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From: Kito Cheng <kito@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2440] RISC-V: Fix division instructions for `m` with `zmmul` extension. Date: Mon, 5 Sep 2022 13:46:16 +0000 (GMT) [thread overview] Message-ID: <20220905134616.206013857036@sourceware.org> (raw) https://gcc.gnu.org/g:ae97ba1efcd66d73d3631addf4c09f55e12d34f5 commit r13-2440-gae97ba1efcd66d73d3631addf4c09f55e12d34f5 Author: Kito Cheng <kito.cheng@sifive.com> Date: Mon Sep 5 21:36:45 2022 +0800 RISC-V: Fix division instructions for `m` with `zmmul` extension. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_option_override): Fix wrong condition for MASK_DIV and simplify incompatible checking. * config/riscv/riscv.md (muldi3): Adding parentheses. Diff: --- gcc/config/riscv/riscv.cc | 8 ++------ gcc/config/riscv/riscv.md | 2 +- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index b5252b41df7..675d92c0961 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5277,14 +5277,10 @@ riscv_option_override (void) /* The presence of the M extension implies that division instructions are present, so include them unless explicitly disabled. */ if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0) - if(!TARGET_ZMMUL) - target_flags |= MASK_DIV; + target_flags |= MASK_DIV; else if (!TARGET_MUL && TARGET_DIV) error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension"); - - if(TARGET_ZMMUL && !TARGET_MUL && TARGET_DIV) - warning (0, "%<-mdiv%> cannot be used when %<ZMMUL%> extension is present"); - + /* Likewise floating-point division and square root. */ if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0) target_flags |= MASK_FDIV; diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d2dfde28e31..014206fb8bd 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -752,7 +752,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (match_operand:DI 1 "register_operand" " r") (match_operand:DI 2 "register_operand" " r")))] - "TARGET_ZMMUL || TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" "mul\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")])
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