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From: Christophe Lyon <clyon@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2533] arm: Fix constant immediates predicates and constraints for some MVE builtins Date: Thu, 8 Sep 2022 09:44:37 +0000 (GMT) [thread overview] Message-ID: <20220908094437.9234A3858406@sourceware.org> (raw) https://gcc.gnu.org/g:c3fb6658c7670e446f2fd00984404d971e416b3c commit r13-2533-gc3fb6658c7670e446f2fd00984404d971e416b3c Author: Christophe Lyon <christophe.lyon@arm.com> Date: Tue Sep 6 16:08:36 2022 +0000 arm: Fix constant immediates predicates and constraints for some MVE builtins Several MVE builtins incorrectly use the same predicate/constraint pair for several modes, which does not match the specification. This patch uses the appropriate iterator instead. 2022-09-06 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/mve.md (mve_vqshluq_n_s<mode>): Use MVE_pred/MVE_constraint instead of mve_imm_7/Ra. (mve_vqshluq_m_n_s<mode>): Likewise. (mve_vqrshrnbq_n_<supf><mode>): Use MVE_pred3/MVE_constraint3 instead of mve_imm_8/Rb. (mve_vqrshrunbq_n_s<mode>): Likewise. (mve_vqrshrntq_n_<supf><mode>): Likewise. (mve_vqrshruntq_n_s<mode>): Likewise. (mve_vrshrnbq_n_<supf><mode>): Likewise. (mve_vrshrntq_n_<supf><mode>): Likewise. (mve_vqrshrnbq_m_n_<supf><mode>): Likewise. (mve_vqrshrntq_m_n_<supf><mode>): Likewise. (mve_vrshrnbq_m_n_<supf><mode>): Likewise. (mve_vrshrntq_m_n_<supf><mode>): Likewise. (mve_vqrshrunbq_m_n_s<mode>): Likewise. (mve_vsriq_n_<supf><mode): Use MVE_pred2/MVE_constraint2 instead of mve_imm_selective_upto_8/Rg. (mve_vsriq_m_n_<supf><mode>): Likewise. Diff: --- gcc/config/arm/mve.md | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index c4dec01baac..714178609f7 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1624,7 +1624,7 @@ [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:SI 2 "mve_imm_7" "Ra")] + (match_operand:SI 2 "<MVE_pred>" "<MVE_constraint>")] VQSHLUQ_N_S)) ] "TARGET_HAVE_MVE" @@ -2615,7 +2615,7 @@ (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] VQRSHRNBQ_N)) ] "TARGET_HAVE_MVE" @@ -2630,7 +2630,7 @@ (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] VQRSHRUNBQ_N_S)) ] "TARGET_HAVE_MVE" @@ -3570,7 +3570,7 @@ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")] + (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")] VSRIQ_N)) ] "TARGET_HAVE_MVE" @@ -4473,7 +4473,7 @@ (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] VQRSHRNTQ_N)) ] "TARGET_HAVE_MVE" @@ -4489,7 +4489,7 @@ (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] VQRSHRUNTQ_N_S)) ] "TARGET_HAVE_MVE" @@ -4777,7 +4777,7 @@ (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] VRSHRNBQ_N)) ] "TARGET_HAVE_MVE" @@ -4793,7 +4793,7 @@ (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] VRSHRNTQ_N)) ] "TARGET_HAVE_MVE" @@ -4987,7 +4987,7 @@ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_7" "Ra") + (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>") (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQSHLUQ_M_N_S)) ] @@ -5019,7 +5019,7 @@ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg") + (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VSRIQ_M_N)) ] @@ -6138,7 +6138,7 @@ (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRSHRNBQ_M_N)) ] @@ -6155,7 +6155,7 @@ (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRSHRNTQ_M_N)) ] @@ -6223,7 +6223,7 @@ (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VRSHRNBQ_M_N)) ] @@ -6240,7 +6240,7 @@ (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VRSHRNTQ_M_N)) ] @@ -6461,7 +6461,7 @@ (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRSHRUNBQ_M_N_S)) ]
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