[gcc(refs/users/meissner/heads/work100)] Undo unintended patch.

[gcc(refs/users/meissner/heads/work100)] Undo unintended patch.

[Michael Meissner]

https://gcc.gnu.org/g:fd08d70bce4acd72bc41df1fe15717c1cfbfb6b6

commit fd08d70bce4acd72bc41df1fe15717c1cfbfb6b6
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Sep 8 14:09:03 2022 -0400

    Undo unintended patch.
    
    2022-09-08   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * gcc/config/rs6000/rs6000.md: Restore original file.
            * gcc/config/rs6000/rs6000.cc: Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc |   4 +-
 gcc/config/rs6000/rs6000.md | 177 ++++++++++++++++++++++++++++++++------------
 2 files changed, 131 insertions(+), 50 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6f822434ab0..a656cb32a47 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -11045,11 +11045,11 @@ init_float128_ieee (machine_mode mode)
       set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
       set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
 
-      set_conv_libfunc (trunc_optab, mode, IFmode, "__trunctfkf2");
+      set_conv_libfunc (sext_optab, mode, IFmode, "__trunctfkf2");
       if (mode != TFmode && FLOAT128_IBM_P (TFmode))
 	set_conv_libfunc (sext_optab, mode, TFmode, "__trunctfkf2");
 
-      set_conv_libfunc (sext_optab, IFmode, mode, "__extendkftf2");
+      set_conv_libfunc (trunc_optab, IFmode, mode, "__extendkftf2");
       if (mode != TFmode && FLOAT128_IBM_P (TFmode))
 	set_conv_libfunc (trunc_optab, TFmode, mode, "__extendkftf2");
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 838d38616b7..ad5a4cf2ef8 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -543,6 +543,12 @@
 ; Iterator for 128-bit VSX types for pack/unpack
 (define_mode_iterator FMOVE128_VSX [V1TI KF])
 
+; Iterators for converting to/from TFmode
+(define_mode_iterator IFKF [IF KF])
+
+; Constraints for moving IF/KFmode.
+(define_mode_attr IFKF_reg [(IF "d") (KF "wa")])
+
 ; Whether a floating point move is ok, don't allow SD without hardware FP
 (define_mode_attr fmove_ok [(SF "")
 			    (DF "")
@@ -9091,65 +9097,106 @@
   "xxlor %x0,%x1,%x2"
   [(set_attr "type" "veclogical")])
 
-;; Float128 conversion functions.  We only define the 'conversions' between two
-;; formats that use the same representation.  We call the library function to
-;; convert between IEEE 128-bit and IBM 128-bit.  We can't do these moves by
-;; using a SUBREG before register allocation.  We set up the moves to prefer
-;; the output register being the same as the input register, which would enable
-;; the move to be deleted completely.
-(define_insn_and_split "extendkftf2"
-  [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa")
-	(float_extend:TF (match_operand:KF 1 "gpc_reg_operand" "0,wa")))]
-  "TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (TFmode)"
-  "#"
-  "&& reload_completed"
-  [(set (match_dup 0)
-	(match_dup 2))]
+;; Float128 conversion functions.  These expand to library function calls.
+;; We use expand to convert from IBM double double to IEEE 128-bit
+;; and trunc for the opposite.
+(define_expand "extendiftf2"
+  [(set (match_operand:TF 0 "gpc_reg_operand")
+	(float_extend:TF (match_operand:IF 1 "gpc_reg_operand")))]
+  "TARGET_FLOAT128_TYPE"
 {
-  operands[2] = gen_lowpart (TFmode, operands[1]);
-}
-  [(set_attr "type" "veclogical")])
+  rs6000_expand_float128_convert (operands[0], operands[1], false);
+  DONE;
+})
 
-(define_insn_and_split "trunctfkf2"
-  [(set (match_operand:KF 0 "gpc_reg_operand" "=wa,wa")
-	(float_truncate:KF (match_operand:TF 1 "gpc_reg_operand" "0,wa")))]
-  "TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (TFmode)"
-  "#"
-  "&& reload_completed"
-  [(set (match_dup 0)
-	(match_dup 2))]
+(define_expand "extendifkf2"
+  [(set (match_operand:KF 0 "gpc_reg_operand")
+	(float_extend:KF (match_operand:IF 1 "gpc_reg_operand")))]
+  "TARGET_FLOAT128_TYPE"
 {
-  operands[2] = gen_lowpart (KFmode, operands[1]);
-}
-  [(set_attr "type" "veclogical")])
+  rs6000_expand_float128_convert (operands[0], operands[1], false);
+  DONE;
+})
+
+(define_expand "extendtfkf2"
+  [(set (match_operand:KF 0 "gpc_reg_operand")
+	(float_extend:KF (match_operand:TF 1 "gpc_reg_operand")))]
+  "TARGET_FLOAT128_TYPE"
+{
+  rs6000_expand_float128_convert (operands[0], operands[1], false);
+  DONE;
+})
+
+(define_expand "extendtfif2"
+  [(set (match_operand:IF 0 "gpc_reg_operand")
+	(float_extend:IF (match_operand:TF 1 "gpc_reg_operand")))]
+  "TARGET_FLOAT128_TYPE"
+{
+  rs6000_expand_float128_convert (operands[0], operands[1], false);
+  DONE;
+})
+
+(define_expand "trunciftf2"
+  [(set (match_operand:TF 0 "gpc_reg_operand")
+	(float_truncate:TF (match_operand:IF 1 "gpc_reg_operand")))]
+  "TARGET_FLOAT128_TYPE"
+{
+  rs6000_expand_float128_convert (operands[0], operands[1], false);
+  DONE;
+})
+
+(define_expand "truncifkf2"
+  [(set (match_operand:KF 0 "gpc_reg_operand")
+	(float_truncate:KF (match_operand:IF 1 "gpc_reg_operand")))]
+  "TARGET_FLOAT128_TYPE"
+{
+  rs6000_expand_float128_convert (operands[0], operands[1], false);
+  DONE;
+})
+
+(define_expand "trunckftf2"
+  [(set (match_operand:TF 0 "gpc_reg_operand")
+	(float_truncate:TF (match_operand:KF 1 "gpc_reg_operand")))]
+  "TARGET_FLOAT128_TYPE"
+{
+  rs6000_expand_float128_convert (operands[0], operands[1], false);
+  DONE;
+})
+
+(define_expand "trunctfif2"
+  [(set (match_operand:IF 0 "gpc_reg_operand")
+	(float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))]
+  "TARGET_FLOAT128_TYPE"
+{
+  rs6000_expand_float128_convert (operands[0], operands[1], false);
+  DONE;
+})
 
-(define_insn_and_split "extendtfif2"
-  [(set (match_operand:IF 0 "gpc_reg_operand" "=wa,wa,r,r")
-	(float_extend:IF (match_operand:TF 1 "gpc_reg_operand" "0,wa,0,r")))]
-  "TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)"
+(define_insn_and_split "*extend<mode>tf2_internal"
+  [(set (match_operand:TF 0 "gpc_reg_operand" "=<IFKF_reg>")
+	(float_extend:TF
+	 (match_operand:IFKF 1 "gpc_reg_operand" "<IFKF_reg>")))]
+   "TARGET_FLOAT128_TYPE
+    && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (<MODE>mode)"
   "#"
   "&& reload_completed"
-  [(set (match_dup 0)
-	(match_dup 2))]
+  [(set (match_dup 0) (match_dup 2))]
 {
-  operands[2] = gen_lowpart (IFmode, operands[1]);
-}
-  [(set_attr "num_insns" "2")
-   (set_attr "length" "8")])
+  operands[2] = gen_rtx_REG (TFmode, REGNO (operands[1]));
+})
 
-(define_insn_and_split "extendiftf2"
-  [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa,r,r")
-	(float_extend:TF (match_operand:IF 1 "gpc_reg_operand" "0,wa,0,r")))]
-  "TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)"
+(define_insn_and_split "*extendtf<mode>2_internal"
+  [(set (match_operand:IFKF 0 "gpc_reg_operand" "=<IFKF_reg>")
+	(float_extend:IFKF
+	 (match_operand:TF 1 "gpc_reg_operand" "<IFKF_reg>")))]
+   "TARGET_FLOAT128_TYPE
+    && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (<MODE>mode)"
   "#"
   "&& reload_completed"
-  [(set (match_dup 0)
-	(match_dup 2))]
+  [(set (match_dup 0) (match_dup 2))]
 {
-  operands[2] = gen_lowpart (TFmode, operands[1]);
-}
-  [(set_attr "num_insns" "2")
-   (set_attr "length" "8")])
+  operands[2] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
+})
 
 \f
 ;; Reload helper functions used by rs6000_secondary_reload.  The patterns all
@@ -14863,6 +14910,40 @@
   [(set_attr "type" "vecfloat")
    (set_attr "size" "128")])
 
+;; Conversion between KFmode and TFmode if TFmode is ieee 128-bit floating
+;; point is a simple copy.
+(define_insn_and_split "extendkftf2"
+  [(set (match_operand:TF 0 "vsx_register_operand" "=wa,?wa")
+	(float_extend:TF (match_operand:KF 1 "vsx_register_operand" "0,wa")))]
+  "TARGET_FLOAT128_TYPE && TARGET_IEEEQUAD"
+  "@
+   #
+   xxlor %x0,%x1,%x1"
+  "&& reload_completed  && REGNO (operands[0]) == REGNO (operands[1])"
+  [(const_int 0)]
+{
+  emit_note (NOTE_INSN_DELETED);
+  DONE;
+}
+  [(set_attr "type" "*,veclogical")
+   (set_attr "length" "0,4")])
+
+(define_insn_and_split "trunctfkf2"
+  [(set (match_operand:KF 0 "vsx_register_operand" "=wa,?wa")
+	(float_extend:KF (match_operand:TF 1 "vsx_register_operand" "0,wa")))]
+  "TARGET_FLOAT128_TYPE && TARGET_IEEEQUAD"
+  "@
+   #
+   xxlor %x0,%x1,%x1"
+  "&& reload_completed  && REGNO (operands[0]) == REGNO (operands[1])"
+  [(const_int 0)]
+{
+  emit_note (NOTE_INSN_DELETED);
+  DONE;
+}
+  [(set_attr "type" "*,veclogical")
+   (set_attr "length" "0,4")])
+
 (define_insn "trunc<mode>df2_hw"
   [(set (match_operand:DF 0 "altivec_register_operand" "=v")
 	(float_truncate:DF