[gcc r13-2580] xtensa: constantsynth: Add new 3-insns synthesis pattern

[gcc r13-2580] xtensa: constantsynth: Add new 3-insns synthesis pattern

[Max Filippov]

https://gcc.gnu.org/g:75e5cc9c3aba943819c284902b3792f7150749cf

commit r13-2580-g75e5cc9c3aba943819c284902b3792f7150749cf
Author: Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
Date:   Sat Sep 10 18:29:45 2022 +0900

    xtensa: constantsynth: Add new 3-insns synthesis pattern
    
    This patch adds a new 3-instructions constant synthesis pattern:
    
    - A value that can fit into a signed 12-bit after a number of either bitwise
      left or right rotations:
        => "MOVI(.N) Ax, simm12" + "SSAI (1 ... 11) or (21 ... 31)"
            + "SRC Ax, Ax, Ax"
    
    gcc/ChangeLog:
    
            * config/xtensa/xtensa.cc (xtensa_constantsynth):
            Add new pattern for the abovementioned case.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/xtensa/constsynth_3insns.c (test_4):
            Add new test function.

Diff:
---
 gcc/config/xtensa/xtensa.cc                        | 31 ++++++++++++++++++++++
 .../gcc.target/xtensa/constsynth_3insns.c          | 11 ++++++++
 2 files changed, 42 insertions(+)

diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index 0f586b09dfb..ac52c015a94 100644
--- a/gcc/config/xtensa/xtensa.cc
+++ b/gcc/config/xtensa/xtensa.cc
@@ -1142,6 +1142,37 @@ xtensa_constantsynth (rtx dst, HOST_WIDE_INT srcval)
 					  xtensa_constantsynth_rtx_ADDSUBX,
 					  divisor))
 	    return 1;
+
+      /* loading simm12 followed by left/right bitwise rotation:
+	 MOVI + SSAI + SRC.  */
+      if ((srcval & 0x001FF800) == 0
+	  || (srcval & 0x001FF800) == 0x001FF800)
+	{
+	  int32_t v;
+
+	  for (shift = 1; shift < 12; ++shift)
+	    {
+	      v = (int32_t)(((uint32_t)srcval >> shift)
+			    | ((uint32_t)srcval << (32 - shift)));
+	      if (xtensa_simm12b(v))
+		{
+		  emit_move_insn (dst, GEN_INT (v));
+		  emit_insn (gen_rotlsi3 (dst, dst, GEN_INT (shift)));
+		  return 1;
+		}
+	    }
+	  for (shift = 1; shift < 12; ++shift)
+	    {
+	      v = (int32_t)(((uint32_t)srcval << shift)
+			    | ((uint32_t)srcval >> (32 - shift)));
+	      if (xtensa_simm12b(v))
+		{
+		  emit_move_insn (dst, GEN_INT (v));
+		  emit_insn (gen_rotrsi3 (dst, dst, GEN_INT (shift)));
+		  return 1;
+		}
+	    }
+	}
     }
 
   return 0;
diff --git a/gcc/testsuite/gcc.target/xtensa/constsynth_3insns.c b/gcc/testsuite/gcc.target/xtensa/constsynth_3insns.c
index f3c4a1c7c15..831288c7ddd 100644
--- a/gcc/testsuite/gcc.target/xtensa/constsynth_3insns.c
+++ b/gcc/testsuite/gcc.target/xtensa/constsynth_3insns.c
@@ -21,4 +21,15 @@ void test_3(int *p)
   *p = 192437;
 }
 
+struct foo
+{
+  unsigned int b : 10;
+  unsigned int g : 11;
+  unsigned int r : 11;
+};
+void test_4(struct foo *p, unsigned int v)
+{
+  p->g = v;
+}
+
 /* { dg-final { scan-assembler-not "l32r" } } */