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* [gcc(refs/users/meissner/heads/dmf001)] Add initial DMR register support.
@ 2022-10-07 23:07 Michael Meissner
0 siblings, 0 replies; only message in thread
From: Michael Meissner @ 2022-10-07 23:07 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:15aec48a845dfd4737a3d26f912a51619c6a8b42
commit 15aec48a845dfd4737a3d26f912a51619c6a8b42
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Oct 7 19:06:26 2022 -0400
Add initial DMR register support.
2022-10-07 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/constraints.md (wD): New constraint.
* config/rs6000/predicates.md (dmf_operand): New predicate.
* config/rs6000/rs6000-modes.def (TDOmode): New opaque mode.
* config/rs6000/rs6000.cc (rs6000_reg_type): Add support for DMF
registers.
(rs6000_reload_reg_type): Likewise.
(LAST_RELOAD_REG_CLASS): Likewise.
(reload_reg_map): Likewise.
(addr_mask_type): Grow to 16 bits.
(RELOAD_REG_NO_MEMORY): New RELOAD_REG macro.
(rs6000_reg_names): Add DMR registers.
(alt_reg_names): Likewise.
(rs6000_hard_regno_nregs_internal): Add support for DMF registers.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_modes_tieable_p): Likewise.
(rs6000_debug_addr_mask): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
* config/rs6000/rs6000.h (UNITS_PER_DMF_WORD): New macro.
(FIRST_PSEUDO_REGISTER): Add support for DMF registers.
(FIXED_REGISTERS): Likewise.
(CALL_REALLY_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(DMF_REGNO_P): New macro.
(enum reg_class): Likewise.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(REGISTER_NAMES): Likewise.
(ADDITIONAL_REGISTER_NAMES): Likewise.
* config/rs6000/rs6000.md (FIRST_DMF_REGNO): New constant.
(LAST_DMF_REGNO): New constant.
(isa attribute): Add dmf and mma_fpr attributes.
(enabled attribute): Add support for dmf and mma_fpr attributes.
Diff:
---
gcc/config/rs6000/constraints.md | 3 ++
gcc/config/rs6000/predicates.md | 13 ++++++
gcc/config/rs6000/rs6000-modes.def | 4 ++
gcc/config/rs6000/rs6000.cc | 91 +++++++++++++++++++++++++++++---------
gcc/config/rs6000/rs6000.h | 37 +++++++++++++---
gcc/config/rs6000/rs6000.md | 10 ++++-
6 files changed, 131 insertions(+), 27 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 54fef8d9996..af1a0b2c563 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -107,6 +107,9 @@
(match_test "TARGET_P8_VECTOR")
(match_operand 0 "s5bit_cint_operand")))
+(define_register_constraint "wD" "DMF_REGS"
+ "DMF register.")
+
(define_constraint "wE"
"@internal Vector constant that can be loaded with the XXSPLTIB instruction."
(match_test "xxspltib_constant_nosplit (op, mode)"))
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index b1fcc69bb60..51aa0f7449e 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -186,6 +186,19 @@
return VLOGICAL_REGNO_P (REGNO (op));
})
+;; Return 1 if op is a DMF register
+(define_predicate "dmf_operand"
+ (match_operand 0 "register_operand")
+{
+ if (!REG_P (op))
+ return 0;
+
+ if (!HARD_REGISTER_P (op))
+ return 1;
+
+ return DMF_REGNO_P (REGNO (op));
+})
+
;; Return 1 if op is the carry register.
(define_predicate "ca_operand"
(match_operand 0 "register_operand")
diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def
index 8ef910869c5..a1384d5dd91 100644
--- a/gcc/config/rs6000/rs6000-modes.def
+++ b/gcc/config/rs6000/rs6000-modes.def
@@ -86,3 +86,7 @@ PARTIAL_INT_MODE (TI, 128, PTI);
/* Modes used by __vector_pair and __vector_quad. */
OPAQUE_MODE (OO, 32);
OPAQUE_MODE (XO, 64);
+
+/* Modes used by __dmr. */
+OPAQUE_MODE (TDO, 128);
+
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 714dfc1ea4e..eb94bb27c78 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -290,7 +290,8 @@ enum rs6000_reg_type {
ALTIVEC_REG_TYPE,
FPR_REG_TYPE,
SPR_REG_TYPE,
- CR_REG_TYPE
+ CR_REG_TYPE,
+ DMF_REG_TYPE
};
/* Map register class to register type. */
@@ -304,22 +305,23 @@ static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
/* Register classes we care about in secondary reload or go if legitimate
- address. We only need to worry about GPR, FPR, and Altivec registers here,
- along an ANY field that is the OR of the 3 register classes. */
+ address. We only need to worry about GPR, FPR, Altivec, and DMF registers
+ here, along an ANY field that is the OR of the 4 register classes. */
enum rs6000_reload_reg_type {
RELOAD_REG_GPR, /* General purpose registers. */
RELOAD_REG_FPR, /* Traditional floating point regs. */
RELOAD_REG_VMX, /* Altivec (VMX) registers. */
- RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
+ RELOAD_REG_DMF, /* DMF registers. */
+ RELOAD_REG_ANY, /* OR of GPR/FPR/VMX/DMF masks. */
N_RELOAD_REG
};
-/* For setting up register classes, loop through the 3 register classes mapping
+/* For setting up register classes, loop through the 4 register classes mapping
into real registers, and skip the ANY class, which is just an OR of the
bits. */
#define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
-#define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
+#define LAST_RELOAD_REG_CLASS RELOAD_REG_DMF
/* Map reload register type to a register in the register class. */
struct reload_reg_map_type {
@@ -331,22 +333,24 @@ static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
{ "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
{ "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
{ "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
+ { "DMF", FIRST_DMF_REGNO }, /* RELOAD_REG_DMF. */
{ "Any", -1 }, /* RELOAD_REG_ANY. */
};
/* Mask bits for each register class, indexed per mode. Historically the
compiler has been more restrictive which types can do PRE_MODIFY instead of
PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
-typedef unsigned char addr_mask_type;
-
-#define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
-#define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
-#define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
-#define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
-#define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
-#define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
-#define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
-#define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
+typedef unsigned short addr_mask_type;
+
+#define RELOAD_REG_VALID 0x001 /* Mode valid in register.. */
+#define RELOAD_REG_MULTIPLE 0x002 /* Mode takes multiple registers. */
+#define RELOAD_REG_INDEXED 0x004 /* Reg+reg addressing. */
+#define RELOAD_REG_OFFSET 0x008 /* Reg+offset addressing. */
+#define RELOAD_REG_PRE_INCDEC 0x010 /* PRE_INC/PRE_DEC valid. */
+#define RELOAD_REG_PRE_MODIFY 0x020 /* PRE_MODIFY valid. */
+#define RELOAD_REG_AND_M16 0x040 /* AND -16 addressing. */
+#define RELOAD_REG_QUAD_OFFSET 0x080 /* quad offset is limited. */
+#define RELOAD_REG_NO_MEMORY 0x100 /* no memory access. */
/* Register type masks based on the type, of valid addressing modes. */
struct rs6000_reg_addr {
@@ -1223,6 +1227,8 @@ char rs6000_reg_names[][8] =
"0", "1", "2", "3", "4", "5", "6", "7",
/* vrsave vscr sfp */
"vrsave", "vscr", "sfp",
+ /* DMFs */
+ "0", "1", "2", "3", "4", "5", "6", "7",
};
#ifdef TARGET_REGNAMES
@@ -1249,6 +1255,8 @@ static const char alt_reg_names[][8] =
"%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
/* vrsave vscr sfp */
"vrsave", "vscr", "sfp",
+ /* DMFs */
+ "%dmr0", "%dmr1", "%dmr2", "%dmr3", "%dmr4", "%dmr5", "%dmr6", "%dmr7",
};
#endif
@@ -1813,13 +1821,18 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
128-bit floating point that can go in vector registers, which has VSX
memory addressing. */
if (FP_REGNO_P (regno))
- reg_size = (VECTOR_MEM_VSX_P (mode) || VECTOR_ALIGNMENT_P (mode)
+ reg_size = (VECTOR_MEM_VSX_P (mode)
+ || VECTOR_ALIGNMENT_P (mode)
+ || mode == TDOmode
? UNITS_PER_VSX_WORD
: UNITS_PER_FP_WORD);
else if (ALTIVEC_REGNO_P (regno))
reg_size = UNITS_PER_ALTIVEC_WORD;
+ else if (DMF_REGNO_P (regno))
+ reg_size = UNITS_PER_DMF_WORD;
+
else
reg_size = UNITS_PER_WORD;
@@ -1841,9 +1854,21 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
if (mode == OOmode)
return (TARGET_MMA && VSX_REGNO_P (regno) && (regno & 1) == 0);
- /* MMA accumulator modes need FPR registers divisible by 4. */
+ /* MMA accumulator modes need FPR registers divisible by 4 or they need DMF
+ registers. */
if (mode == XOmode)
- return (TARGET_MMA && FP_REGNO_P (regno) && (regno & 3) == 0);
+ return ((TARGET_MMA && FP_REGNO_P (regno) && (regno & 3) == 0)
+ || (TARGET_DMF && DMF_REGNO_P (regno)));
+
+ /* DMF register modes need DMF registers or VSX registers divisible by 4. */
+ if (mode == TDOmode)
+ return (TARGET_DMF
+ && (DMF_REGNO_P (regno)
+ || (VSX_REGNO_P (regno) && (regno & 3) == 0)));
+
+ /* No other types other than XOmode or TDOmode can go in DMFs. */
+ if (DMF_REGNO_P (regno))
+ return 0;
/* PTImode can only go in GPRs. Quad word memory operations require even/odd
register combinations, and use PTImode where we need to deal with quad
@@ -1960,7 +1985,8 @@ static bool
rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
{
if (mode1 == PTImode || mode1 == OOmode || mode1 == XOmode
- || mode2 == PTImode || mode2 == OOmode || mode2 == XOmode)
+ || mode2 == PTImode || mode2 == OOmode || mode2 == XOmode
+ || mode1 == TDOmode || mode2 == TDOmode)
return mode1 == mode2;
if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
@@ -2106,7 +2132,7 @@ rs6000_debug_vector_unit (enum rs6000_vector v)
DEBUG_FUNCTION char *
rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
{
- static char ret[8];
+ static char ret[10];
char *p = ret;
if ((mask & RELOAD_REG_VALID) != 0)
@@ -2146,6 +2172,11 @@ rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
else if (keep_spaces)
*p++ = ' ';
+ if ((mask & RELOAD_REG_NO_MEMORY) != 0)
+ *p++ = 'M';
+ else if (keep_spaces)
+ *p++ = ' ';
+
*p = '\0';
return ret;
@@ -2251,6 +2282,7 @@ rs6000_debug_reg_global (void)
V4DFmode,
OOmode,
XOmode,
+ TDOmode,
CCmode,
CCUNSmode,
CCEQmode,
@@ -2286,6 +2318,7 @@ rs6000_debug_reg_global (void)
rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
LAST_ALTIVEC_REGNO,
"vs");
+ rs6000_debug_reg_print (FIRST_DMF_REGNO, LAST_DMF_REGNO, "dmf");
rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
@@ -2610,6 +2643,18 @@ rs6000_setup_reg_addr_masks (void)
addr_mask = 0;
reg = reload_reg_map[rc].reg;
+ /* Special case DMF registers. */
+ if (rc == RELOAD_REG_DMF)
+ {
+ if (TARGET_DMF && (m2 == XOmode || m2 == TDOmode))
+ {
+ addr_mask = RELOAD_REG_VALID | RELOAD_REG_NO_MEMORY;
+ reg_addr[m].addr_mask[rc] = addr_mask;
+ any_addr_mask |= addr_mask;
+ }
+ continue;
+ }
+
/* Can mode values go in the GPR/FPR/Altivec registers? */
if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
{
@@ -2760,6 +2805,9 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
rs6000_regno_regclass[r] = CR_REGS;
+ for (r = FIRST_DMF_REGNO; r <= LAST_DMF_REGNO; ++r)
+ rs6000_regno_regclass[r] = DMF_REGS;
+
rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
rs6000_regno_regclass[CA_REGNO] = NO_REGS;
@@ -2784,6 +2832,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
+ reg_class_to_reg_type[(int)DMF_REGS] = DMF_REG_TYPE;
if (TARGET_VSX)
{
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 0df5911d852..d47337f7c51 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -662,6 +662,7 @@ extern unsigned char rs6000_recip_bits[];
#define UNITS_PER_FP_WORD 8
#define UNITS_PER_ALTIVEC_WORD 16
#define UNITS_PER_VSX_WORD 16
+#define UNITS_PER_DMF_WORD 128
/* Type used for ptrdiff_t, as a string used in a declaration. */
#define PTRDIFF_TYPE "int"
@@ -789,7 +790,7 @@ enum data_align { align_abi, align_opt, align_both };
Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
pointer, which is eventually eliminated in favor of SP or FP. */
-#define FIRST_PSEUDO_REGISTER 111
+#define FIRST_PSEUDO_REGISTER 119
/* Use standard DWARF numbering for DWARF debugging information. */
#define DEBUGGER_REGNO(REGNO) rs6000_debugger_regno ((REGNO), 0)
@@ -826,7 +827,9 @@ enum data_align { align_abi, align_opt, align_both };
/* cr0..cr7 */ \
0, 0, 0, 0, 0, 0, 0, 0, \
/* vrsave vscr sfp */ \
- 1, 1, 1 \
+ 1, 1, 1, \
+ /* DMF registers. */ \
+ 0, 0, 0, 0, 0, 0, 0, 0 \
}
/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
@@ -850,7 +853,9 @@ enum data_align { align_abi, align_opt, align_both };
/* cr0..cr7 */ \
1, 1, 0, 0, 0, 1, 1, 1, \
/* vrsave vscr sfp */ \
- 0, 0, 0 \
+ 0, 0, 0, \
+ /* DMF registers. */ \
+ 0, 0, 0, 0, 0, 0, 0, 0 \
}
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
@@ -887,6 +892,7 @@ enum data_align { align_abi, align_opt, align_both };
v2 (not saved; incoming vector arg reg; return value)
v19 - v14 (not saved or used for anything)
v31 - v20 (saved; order given to save least number)
+ dmr0 - dmr7 (not saved)
vrsave, vscr (fixed)
sfp (fixed)
*/
@@ -929,6 +935,9 @@ enum data_align { align_abi, align_opt, align_both };
66, \
83, 82, 81, 80, 79, 78, \
95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \
+ /* DMF registers. */ \
+ 111, 112, 113, 114, 115, 116, 117, 118, \
+ /* Vrsave, vscr, sfp. */ \
108, 109, \
110 \
}
@@ -955,6 +964,9 @@ enum data_align { align_abi, align_opt, align_both };
/* True if register is a VSX register. */
#define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
+/* True if register is a DMF register. */
+#define DMF_REGNO_P(N) ((N) >= FIRST_DMF_REGNO && (N) <= LAST_DMF_REGNO)
+
/* Alternate name for any vector register supporting floating point, no matter
which instruction set(s) are available. */
#define VFLOAT_REGNO_P(N) \
@@ -1090,6 +1102,7 @@ enum reg_class
FLOAT_REGS,
ALTIVEC_REGS,
VSX_REGS,
+ DMF_REGS,
VRSAVE_REGS,
VSCR_REGS,
GEN_OR_FLOAT_REGS,
@@ -1119,6 +1132,7 @@ enum reg_class
"FLOAT_REGS", \
"ALTIVEC_REGS", \
"VSX_REGS", \
+ "DMF_REGS", \
"VRSAVE_REGS", \
"VSCR_REGS", \
"GEN_OR_FLOAT_REGS", \
@@ -1153,6 +1167,8 @@ enum reg_class
{ 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \
/* VSX_REGS. */ \
{ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
+ /* DMF_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x007f8000 }, \
/* VRSAVE_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \
/* VSCR_REGS. */ \
@@ -1180,7 +1196,7 @@ enum reg_class
/* CA_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \
/* ALL_REGS. */ \
- { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \
+ { 0xffffffff, 0xffffffff, 0xffffffff, 0x007fffff } \
}
/* The same information, inverted:
@@ -2077,7 +2093,16 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
&rs6000_reg_names[108][0], /* vrsave */ \
&rs6000_reg_names[109][0], /* vscr */ \
\
- &rs6000_reg_names[110][0] /* sfp */ \
+ &rs6000_reg_names[110][0], /* sfp */ \
+ \
+ &rs6000_reg_names[111][0], /* dmr0 */ \
+ &rs6000_reg_names[112][0], /* dmr1 */ \
+ &rs6000_reg_names[113][0], /* dmr2 */ \
+ &rs6000_reg_names[114][0], /* dmr3 */ \
+ &rs6000_reg_names[115][0], /* dmr4 */ \
+ &rs6000_reg_names[116][0], /* dmr5 */ \
+ &rs6000_reg_names[117][0], /* dmr6 */ \
+ &rs6000_reg_names[118][0], /* dmr7 */ \
}
/* Table of additional register names to use in user input. */
@@ -2131,6 +2156,8 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
{"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87}, \
{"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91}, \
{"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95}, \
+ {"dmr0", 111}, {"dmr1", 112}, {"dmr2", 113}, {"dmr3", 114}, \
+ {"dmr4", 115}, {"dmr5", 116}, {"dmr6", 117}, {"dmr7", 118}, \
}
/* This is how to output an element of a case-vector that is relative. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3e74a8b4343..287ddd16ecd 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -51,6 +51,8 @@
(VRSAVE_REGNO 108)
(VSCR_REGNO 109)
(FRAME_POINTER_REGNUM 110)
+ (FIRST_DMF_REGNO 111)
+ (LAST_DMF_REGNO 118)
])
;;
@@ -354,7 +356,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,dmf"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,dmf,mma_fpr"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -406,6 +408,12 @@
(and (eq_attr "isa" "dmf")
(match_test "TARGET_DMF"))
(const_int 1)
+
+ ;; mma_fpr is for use on power10 systems where the accumulators overlap
+ ;; with the FPR registers.
+ (and (eq_attr "isa" "mma_fpr")
+ (match_test "TARGET_MMA && !TARGET_DMF"))
+ (const_int 1)
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
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