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* [gcc r13-3274] [AArch64] Improve bit tests [PR105773]
@ 2022-10-13 13:56 Wilco Dijkstra
0 siblings, 0 replies; only message in thread
From: Wilco Dijkstra @ 2022-10-13 13:56 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1cccf644ff92ac1145abdbf255d1862dd787875b
commit r13-3274-g1cccf644ff92ac1145abdbf255d1862dd787875b
Author: Wilco Dijkstra <wdijkstr@arm.com>
Date: Thu Oct 13 14:41:55 2022 +0100
[AArch64] Improve bit tests [PR105773]
Since AArch64 sets all flags on logical operations, comparisons with zero
can be combined into an AND even if the condition is LE or GT. Add a new
CC_NZV mode used by ANDS/BICS/TST instructions.
gcc/
PR target/105773
* config/aarch64/aarch64.cc (aarch64_select_cc_mode): Allow
GT/LE for merging compare with zero into AND.
(aarch64_get_condition_code_1): Add CC_NZVmode support.
* config/aarch64/aarch64-modes.def: Add CC_NZV.
* config/aarch64/aarch64.md: Use CC_NZV in cmp+and patterns.
gcc/testsuite/
PR target/105773
* gcc.target/aarch64/ands_2.c: Test for ANDS.
* gcc.target/aarch64/bics_2.c: Test for BICS.
* gcc.target/aarch64/tst_2.c: Test for TST.
* gcc.target/aarch64/tst_imm_split_1.c: Fix test.
Diff:
---
gcc/config/aarch64/aarch64-modes.def | 1 +
gcc/config/aarch64/aarch64.cc | 39 +++++++++--
gcc/config/aarch64/aarch64.md | 76 +++++++++++-----------
gcc/testsuite/gcc.target/aarch64/ands_2.c | 30 ++++-----
gcc/testsuite/gcc.target/aarch64/bics_2.c | 24 +++----
gcc/testsuite/gcc.target/aarch64/tst_2.c | 30 ++++-----
gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c | 3 +-
7 files changed, 107 insertions(+), 96 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-modes.def b/gcc/config/aarch64/aarch64-modes.def
index d3c9b74434c..0fd4c32ad0b 100644
--- a/gcc/config/aarch64/aarch64-modes.def
+++ b/gcc/config/aarch64/aarch64-modes.def
@@ -35,6 +35,7 @@ CC_MODE (CCFPE);
CC_MODE (CC_SWP);
CC_MODE (CC_NZC); /* Only N, Z and C bits of condition flags are valid.
(Used with SVE predicate tests.) */
+CC_MODE (CC_NZV); /* Only N, Z and V bits of condition flags are valid. */
CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */
CC_MODE (CC_Z); /* Only Z bit of condition flags is valid. */
CC_MODE (CC_C); /* C represents unsigned overflow of a simple addition. */
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index a8845a55b9e..1d0f994f281 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -11274,7 +11274,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
if (y == const0_rtx && (REG_P (x) || SUBREG_P (x))
&& (code == EQ || code == NE)
&& (mode_x == HImode || mode_x == QImode))
- return CC_NZmode;
+ return CC_Zmode;
/* Similarly, comparisons of zero_extends from shorter modes can
be performed using an ANDS with an immediate mask. */
@@ -11282,15 +11282,29 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
&& (mode_x == SImode || mode_x == DImode)
&& (GET_MODE (XEXP (x, 0)) == HImode || GET_MODE (XEXP (x, 0)) == QImode)
&& (code == EQ || code == NE))
- return CC_NZmode;
+ return CC_Zmode;
+
+ /* Zero extracts support equality comparisons. */
+ if ((mode_x == SImode || mode_x == DImode)
+ && y == const0_rtx
+ && (code_x == ZERO_EXTRACT && CONST_INT_P (XEXP (x, 1))
+ && CONST_INT_P (XEXP (x, 2)))
+ && (code == EQ || code == NE))
+ return CC_Zmode;
+
+ /* ANDS/BICS/TST support equality and all signed comparisons. */
+ if ((mode_x == SImode || mode_x == DImode)
+ && y == const0_rtx
+ && (code_x == AND)
+ && (code == EQ || code == NE || code == LT || code == GE
+ || code == GT || code == LE))
+ return CC_NZVmode;
+ /* ADDS/SUBS correctly set N and Z flags. */
if ((mode_x == SImode || mode_x == DImode)
&& y == const0_rtx
&& (code == EQ || code == NE || code == LT || code == GE)
- && (code_x == PLUS || code_x == MINUS || code_x == AND
- || code_x == NEG
- || (code_x == ZERO_EXTRACT && CONST_INT_P (XEXP (x, 1))
- && CONST_INT_P (XEXP (x, 2)))))
+ && (code_x == PLUS || code_x == MINUS || code_x == NEG))
return CC_NZmode;
/* A compare with a shifted operand. Because of canonicalization,
@@ -11427,6 +11441,19 @@ aarch64_get_condition_code_1 (machine_mode mode, enum rtx_code comp_code)
}
break;
+ case E_CC_NZVmode:
+ switch (comp_code)
+ {
+ case NE: return AARCH64_NE;
+ case EQ: return AARCH64_EQ;
+ case GE: return AARCH64_PL;
+ case LT: return AARCH64_MI;
+ case GT: return AARCH64_GT;
+ case LE: return AARCH64_LE;
+ default: return -1;
+ }
+ break;
+
case E_CC_NZmode:
switch (comp_code)
{
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 0a7633e5dd6..f2e3d905dbb 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4514,8 +4514,8 @@
)
(define_insn "*and<mode>3_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (match_operand:GPI 1 "register_operand" "%r,r")
(match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>"))
(const_int 0)))
@@ -4530,8 +4530,8 @@
;; zero_extend version of above
(define_insn "*andsi3_compare0_uxtw"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:SI (match_operand:SI 1 "register_operand" "%r,r")
(match_operand:SI 2 "aarch64_logical_operand" "r,K"))
(const_int 0)))
@@ -4545,8 +4545,8 @@
)
(define_insn "*and_<SHIFT:optab><mode>3_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (SHIFT:GPI
(match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
@@ -4565,8 +4565,8 @@
;; zero_extend version of above
(define_insn "*and_<SHIFT:optab>si3_compare0_uxtw"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:SI (SHIFT:SI
(match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_shift_imm_si" "n"))
@@ -4770,8 +4770,8 @@
)
(define_insn "*and_one_cmpl<mode>3_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (not:GPI
(match_operand:GPI 1 "register_operand" "r"))
(match_operand:GPI 2 "register_operand" "r"))
@@ -4785,8 +4785,8 @@
;; zero_extend version of above
(define_insn "*and_one_cmplsi3_compare0_uxtw"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:SI (not:SI
(match_operand:SI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" "r"))
@@ -4799,8 +4799,8 @@
)
(define_insn "*and_one_cmpl<mode>3_compare0_no_reuse"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (not:GPI
(match_operand:GPI 0 "register_operand" "r"))
(match_operand:GPI 1 "register_operand" "r"))
@@ -4878,8 +4878,8 @@
)
(define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (not:GPI
(SHIFT:GPI
(match_operand:GPI 1 "register_operand" "r")
@@ -4901,8 +4901,8 @@
;; zero_extend version of above
(define_insn "*and_one_cmpl_<SHIFT:optab>si3_compare0_uxtw"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:SI (not:SI
(SHIFT:SI
(match_operand:SI 1 "register_operand" "r")
@@ -4923,8 +4923,8 @@
)
(define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0_no_reuse"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (not:GPI
(SHIFT:GPI
(match_operand:GPI 0 "register_operand" "r")
@@ -5029,8 +5029,8 @@
")
(define_insn "*and<mode>_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_Z CC_REGNUM)
+ (compare:CC_Z
(match_operand:SHORT 0 "register_operand" "r")
(const_int 0)))]
""
@@ -5039,8 +5039,8 @@
)
(define_insn "*ands<GPI:mode>_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_Z CC_REGNUM)
+ (compare:CC_Z
(zero_extend:GPI (match_operand:SHORT 1 "register_operand" "r"))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
@@ -5051,8 +5051,8 @@
)
(define_insn "*and<mode>3nr_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (match_operand:GPI 0 "register_operand" "%r,r")
(match_operand:GPI 1 "aarch64_logical_operand" "r,<lconst>"))
(const_int 0)))]
@@ -5064,24 +5064,24 @@
)
(define_split
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (match_operand:GPI 0 "register_operand")
(match_operand:GPI 1 "aarch64_mov_imm_operand"))
(const_int 0)))
(clobber (match_operand:SI 2 "register_operand"))]
""
[(set (match_dup 2) (match_dup 1))
- (set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ (set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (match_dup 0)
(match_dup 2))
(const_int 0)))]
)
(define_insn "*and<mode>3nr_compare0_zextract"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_Z CC_REGNUM)
+ (compare:CC_Z
(zero_extract:GPI (match_operand:GPI 0 "register_operand" "r")
(match_operand:GPI 1 "const_int_operand" "n")
(match_operand:GPI 2 "const_int_operand" "n"))
@@ -5102,8 +5102,8 @@
)
(define_insn "*and_<SHIFT:optab><mode>3nr_compare0"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (SHIFT:GPI
(match_operand:GPI 0 "register_operand" "r")
(match_operand:QI 1 "aarch64_shift_imm_<mode>" "n"))
@@ -5119,8 +5119,8 @@
)
(define_split
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ [(set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (SHIFT:GPI
(match_operand:GPI 0 "register_operand")
(match_operand:QI 1 "aarch64_shift_imm_<mode>"))
@@ -5129,8 +5129,8 @@
(clobber (match_operand:SI 3 "register_operand"))]
""
[(set (match_dup 3) (match_dup 2))
- (set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
+ (set (reg:CC_NZV CC_REGNUM)
+ (compare:CC_NZV
(and:GPI (SHIFT:GPI
(match_dup 0)
(match_dup 1))
diff --git a/gcc/testsuite/gcc.target/aarch64/ands_2.c b/gcc/testsuite/gcc.target/aarch64/ands_2.c
index b061b1dfc59..c8763f234c5 100644
--- a/gcc/testsuite/gcc.target/aarch64/ands_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/ands_2.c
@@ -8,8 +8,7 @@ ands_si_test1 (int a, int b, int c)
{
int d = a & b;
- /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
- /* { dg-final { scan-assembler-times "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+ /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
if (d <= 0)
return a + c;
else
@@ -21,12 +20,11 @@ ands_si_test2 (int a, int b, int c)
{
int d = a & 0x99999999;
- /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
- /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
- if (d <= 0)
- return a + c;
- else
+ /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
+ if (d > 0)
return b + d + c;
+ else
+ return a + c;
}
int
@@ -34,8 +32,7 @@ ands_si_test3 (int a, int b, int c)
{
int d = a & (b << 3);
- /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
- /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
if (d <= 0)
return a + c;
else
@@ -49,8 +46,7 @@ ands_di_test1 (s64 a, s64 b, s64 c)
{
s64 d = a & b;
- /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
- /* { dg-final { scan-assembler-times "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+ /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
if (d <= 0)
return a + c;
else
@@ -62,12 +58,11 @@ ands_di_test2 (s64 a, s64 b, s64 c)
{
s64 d = a & 0xaaaaaaaaaaaaaaaall;
- /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
- /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
- if (d <= 0)
- return a + c;
- else
+ /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
+ if (d > 0)
return b + d + c;
+ else
+ return a + c;
}
s64
@@ -75,8 +70,7 @@ ands_di_test3 (s64 a, s64 b, s64 c)
{
s64 d = a & (b << 3);
- /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
- /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
if (d <= 0)
return a + c;
else
diff --git a/gcc/testsuite/gcc.target/aarch64/bics_2.c b/gcc/testsuite/gcc.target/aarch64/bics_2.c
index 9ccae368c12..c1f7e87a612 100644
--- a/gcc/testsuite/gcc.target/aarch64/bics_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/bics_2.c
@@ -8,8 +8,7 @@ bics_si_test1 (int a, int b, int c)
{
int d = a & ~b;
- /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
- /* { dg-final { scan-assembler-times "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+ /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
if (d <= 0)
return a + c;
else
@@ -21,12 +20,11 @@ bics_si_test2 (int a, int b, int c)
{
int d = a & ~(b << 3);
- /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
- /* { dg-final { scan-assembler "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
- if (d <= 0)
- return a + c;
- else
+ /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ if (d > 0)
return b + d + c;
+ else
+ return a + c;
}
typedef long long s64;
@@ -36,8 +34,7 @@ bics_di_test1 (s64 a, s64 b, s64 c)
{
s64 d = a & ~b;
- /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
- /* { dg-final { scan-assembler-times "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+ /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
if (d <= 0)
return a + c;
else
@@ -49,12 +46,11 @@ bics_di_test2 (s64 a, s64 b, s64 c)
{
s64 d = a & ~(b << 3);
- /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
- /* { dg-final { scan-assembler "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
- if (d <= 0)
- return a + c;
- else
+ /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d > 0)
return b + d + c;
+ else
+ return a + c;
}
int
diff --git a/gcc/testsuite/gcc.target/aarch64/tst_2.c b/gcc/testsuite/gcc.target/aarch64/tst_2.c
index c8b28fc5620..3c9bdfd05c4 100644
--- a/gcc/testsuite/gcc.target/aarch64/tst_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/tst_2.c
@@ -8,8 +8,7 @@ tst_si_test1 (int a, int b, int c)
{
int d = a & b;
- /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
- /* { dg-final { scan-assembler-times "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+ /* { dg-final { scan-assembler "tst\tw\[0-9\]+, w\[0-9\]+" } } */
if (d <= 0)
return 12;
else
@@ -21,12 +20,11 @@ tst_si_test2 (int a, int b, int c)
{
int d = a & 0x99999999;
- /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
- /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
- if (d <= 0)
- return 12;
- else
+ /* { dg-final { scan-assembler "tst\tw\[0-9\]+, -1717986919" } } */
+ if (d > 0)
return 18;
+ else
+ return 12;
}
int
@@ -34,8 +32,7 @@ tst_si_test3 (int a, int b, int c)
{
int d = a & (b << 3);
- /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
- /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "tst\tw\[0-9\]+, w\[0-9\]+, lsl 3" } } */
if (d <= 0)
return 12;
else
@@ -49,8 +46,7 @@ tst_di_test1 (s64 a, s64 b, s64 c)
{
s64 d = a & b;
- /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
- /* { dg-final { scan-assembler-times "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+ /* { dg-final { scan-assembler "tst\tx\[0-9\]+, x\[0-9\]+" } } */
if (d <= 0)
return 12;
else
@@ -62,8 +58,7 @@ tst_di_test2 (s64 a, s64 b, s64 c)
{
s64 d = a & 0xaaaaaaaaaaaaaaaall;
- /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
- /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
+ /* { dg-final { scan-assembler "tst\tx\[0-9\]+, -6148914691236517206" } } */
if (d <= 0)
return 12;
else
@@ -75,12 +70,11 @@ tst_di_test3 (s64 a, s64 b, s64 c)
{
s64 d = a & (b << 3);
- /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
- /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
- if (d <= 0)
- return 12;
- else
+ /* { dg-final { scan-assembler "tst\tx\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d > 0)
return 18;
+ else
+ return 12;
}
int
diff --git a/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c b/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c
index 33a2c0f45af..e456e823593 100644
--- a/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c
@@ -14,5 +14,4 @@ g (unsigned char *p)
}
/* { dg-final { scan-assembler-not "and\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+.*" } } */
-/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+" } } */
-/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+, lsr 4" } } */
+/* { dg-final { scan-assembler-times "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+" 2 } } */
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2022-10-13 13:56 [gcc r13-3274] [AArch64] Improve bit tests [PR105773] Wilco Dijkstra
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