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* [gcc(refs/users/meissner/heads/dmf001)] Make wD switch between FPRs and DMFs.
@ 2022-10-14 17:35 Michael Meissner
0 siblings, 0 replies; only message in thread
From: Michael Meissner @ 2022-10-14 17:35 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:e121f43d87674ee698c5d338b67546bbf780fea5
commit e121f43d87674ee698c5d338b67546bbf780fea5
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Oct 14 13:34:59 2022 -0400
Make wD switch between FPRs and DMFs.
2022-10-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* constraints.md (wD): Change wD to be FPR registers for power10 and DMF
registers for DMF systems.
* config/rs6000/mma.md (vvi4i4i8_insn): New int attribute.
(avvi4i4i8_insn): Likewise.
(vvi4i4i2_insn): Likewise.
(avvi4i4i2_insn): Likewise.
(vvi4i4_insn): Likewise.
(avvi4i4_insn): Likewise.
(pvi4i2_insn): Likewise.
(apvi4i2_insn): Likewise.
(vvi4i4i4_insn): Likewise.
(avvi4i4i4_insn): Likewise.
(mma_<vv>): Use wD constraint for accumulator inputs and outputs.
(mma_<avv>): Likewise.
(mma_<pv>): Likewise.
(mma_<apv>): Likewise.
(mma_<vvi4i4i8>): Likewise.
(mma_<avvi4i4i8>): Likewise.
(mma_<vvi4i4i2): Likewise.
(mma_<avvi4i4i2>): Likewise.
(mma_<vvi4i4>): Likewise.
(mma_<avvi4i4>): Likewise.
(mma_<pvi4i2>): Likewise.
(mma_<apvi4i2>): Likewise.
(mma_<vvi4i4i4): Likewise.
(mma_<avvi4i4i4>): Likewise.
* config/rs6000/s6000.cc (rs6000_debug_reg_global): Print what register
class wD implements.
(rs6000_init_hard_regno_mode_ok): Set up to make wD constraint choose
DMF accumualators on DMF systems and FPR registers on MMA systems
without DMF.
(print_operand): Add %d<n> output modifier, to print 'dm' or nothing to
switch MMA instructions being generated.
* config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wD option.
* doc/md.texi (PowerPC constraints): Document the wD constraint.
Diff:
---
gcc/config/rs6000/constraints.md | 4 +-
gcc/config/rs6000/mma.md | 256 +++++++++++++++++++++------------------
gcc/config/rs6000/rs6000.cc | 16 ++-
gcc/config/rs6000/rs6000.h | 1 +
gcc/doc/md.texi | 6 +
5 files changed, 165 insertions(+), 118 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index af1a0b2c563..29bd7e021de 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -107,8 +107,8 @@
(match_test "TARGET_P8_VECTOR")
(match_operand 0 "s5bit_cint_operand")))
-(define_register_constraint "wD" "DMF_REGS"
- "DMF register.")
+(define_register_constraint "wD" "rs6000_constraints[RS6000_CONSTRAINT_wD]"
+ "Register class (FPR or DMF) to use for MMA instructions.")
(define_constraint "wE"
"@internal Vector constant that can be loaded with the XXSPLTIB instruction."
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index c0ac6addac9..fe6f9b692c0 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -227,13 +227,22 @@
(define_int_attr vvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8 "pmxvi4ger8")])
+(define_int_attr vvi4i4i8_insn [(UNSPEC_MMA_PMXVI4GER8 "pm%d0xvi4ger8")])
+
(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP "pmxvi4ger8pp")])
+(define_int_attr avvi4i4i8_insn [(UNSPEC_MMA_PMXVI4GER8PP "pm%d0xvi4ger8pp")])
+
(define_int_attr vvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2 "pmxvi16ger2")
(UNSPEC_MMA_PMXVI16GER2S "pmxvi16ger2s")
(UNSPEC_MMA_PMXVF16GER2 "pmxvf16ger2")
(UNSPEC_MMA_PMXVBF16GER2 "pmxvbf16ger2")])
+(define_int_attr vvi4i4i2_insn [(UNSPEC_MMA_PMXVI16GER2 "pm%d0xvi16ger2")
+ (UNSPEC_MMA_PMXVI16GER2S "pm%d0xvi16ger2s")
+ (UNSPEC_MMA_PMXVF16GER2 "pm%d0xvf16ger2")
+ (UNSPEC_MMA_PMXVBF16GER2 "pm%d0xvbf16ger2")])
+
(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP "pmxvi16ger2pp")
(UNSPEC_MMA_PMXVI16GER2SPP "pmxvi16ger2spp")
(UNSPEC_MMA_PMXVF16GER2PP "pmxvf16ger2pp")
@@ -245,25 +254,55 @@
(UNSPEC_MMA_PMXVBF16GER2NP "pmxvbf16ger2np")
(UNSPEC_MMA_PMXVBF16GER2NN "pmxvbf16ger2nn")])
+(define_int_attr avvi4i4i2_insn [(UNSPEC_MMA_PMXVI16GER2PP "pm%d0xvi16ger2pp")
+ (UNSPEC_MMA_PMXVI16GER2SPP "pm%d0xvi16ger2spp")
+ (UNSPEC_MMA_PMXVF16GER2PP "pm%d0xvf16ger2pp")
+ (UNSPEC_MMA_PMXVF16GER2PN "pm%d0xvf16ger2pn")
+ (UNSPEC_MMA_PMXVF16GER2NP "pm%d0xvf16ger2np")
+ (UNSPEC_MMA_PMXVF16GER2NN "pm%d0xvf16ger2nn")
+ (UNSPEC_MMA_PMXVBF16GER2PP "pm%d0xvbf16ger2pp")
+ (UNSPEC_MMA_PMXVBF16GER2PN "pm%d0xvbf16ger2pn")
+ (UNSPEC_MMA_PMXVBF16GER2NP "pm%d0xvbf16ger2np")
+ (UNSPEC_MMA_PMXVBF16GER2NN "pm%d0xvbf16ger2nn")])
+
(define_int_attr vvi4i4 [(UNSPEC_MMA_PMXVF32GER "pmxvf32ger")])
+(define_int_attr vvi4i4_insn [(UNSPEC_MMA_PMXVF32GER "pm%d0xvf32ger")])
+
(define_int_attr avvi4i4 [(UNSPEC_MMA_PMXVF32GERPP "pmxvf32gerpp")
(UNSPEC_MMA_PMXVF32GERPN "pmxvf32gerpn")
(UNSPEC_MMA_PMXVF32GERNP "pmxvf32gernp")
(UNSPEC_MMA_PMXVF32GERNN "pmxvf32gernn")])
+(define_int_attr avvi4i4_insn [(UNSPEC_MMA_PMXVF32GERPP "pm%d0xvf32gerpp")
+ (UNSPEC_MMA_PMXVF32GERPN "pm%d0xvf32gerpn")
+ (UNSPEC_MMA_PMXVF32GERNP "pm%d0xvf32gernp")
+ (UNSPEC_MMA_PMXVF32GERNN "pm%d0xvf32gernn")])
+
(define_int_attr pvi4i2 [(UNSPEC_MMA_PMXVF64GER "pmxvf64ger")])
+(define_int_attr pvi4i2_insn [(UNSPEC_MMA_PMXVF64GER "pm%d0xvf64ger")])
+
(define_int_attr apvi4i2 [(UNSPEC_MMA_PMXVF64GERPP "pmxvf64gerpp")
(UNSPEC_MMA_PMXVF64GERPN "pmxvf64gerpn")
(UNSPEC_MMA_PMXVF64GERNP "pmxvf64gernp")
(UNSPEC_MMA_PMXVF64GERNN "pmxvf64gernn")])
+(define_int_attr apvi4i2_insn [(UNSPEC_MMA_PMXVF64GERPP "pm%d0xvf64gerpp")
+ (UNSPEC_MMA_PMXVF64GERPN "pm%d0xvf64gerpn")
+ (UNSPEC_MMA_PMXVF64GERNP "pm%d0xvf64gernp")
+ (UNSPEC_MMA_PMXVF64GERNN "pm%d0xvf64gernn")])
+
(define_int_attr vvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4 "pmxvi8ger4")])
+(define_int_attr vvi4i4i4_insn [(UNSPEC_MMA_PMXVI8GER4 "pm%d0xvi8ger4")])
+
(define_int_attr avvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4PP "pmxvi8ger4pp")
(UNSPEC_MMA_PMXVI8GER4SPP "pmxvi8ger4spp")])
+(define_int_attr avvi4i4i4_insn [(UNSPEC_MMA_PMXVI8GER4PP "pm%d0xvi8ger4pp")
+ (UNSPEC_MMA_PMXVI8GER4SPP "pm%d0xvi8ger4spp")])
+
;; Vector pair support. OOmode can only live in VSRs.
(define_expand "movoo"
[(set (match_operand:OO 0 "nonimmediate_operand")
@@ -607,183 +646,170 @@
[(set_attr "type" "mma")])
(define_insn "mma_<vv>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_VV))]
"TARGET_MMA"
- "<vv> %A0,%x1,%x2"
- [(set_attr "type" "mma")
- (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
+ "%d0<vv> %A0,%x1,%x2"
+ [(set_attr "type" "mma")])
(define_insn "mma_<avv>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_AVV))]
"TARGET_MMA"
- "<avv> %A0,%x2,%x3"
- [(set_attr "type" "mma")
- (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
+ "%d0<avv> %A0,%x2,%x3"
+ [(set_attr "type" "mma")])
(define_insn "mma_<pv>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_PV))]
"TARGET_MMA"
- "<pv> %A0,%x1,%x2"
- [(set_attr "type" "mma")
- (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
+ "%d0<pv> %A0,%x1,%x2"
+ [(set_attr "type" "mma")])
(define_insn "mma_<apv>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
- (match_operand:OO 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+ (match_operand:OO 2 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_APV))]
"TARGET_MMA"
- "<apv> %A0,%x2,%x3"
- [(set_attr "type" "mma")
- (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
+ "%d0<apv> %A0,%x2,%x3"
+ [(set_attr "type" "mma")])
(define_insn "mma_<vvi4i4i8>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "u8bit_cint_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "u8bit_cint_operand" "n,n")]
MMA_VVI4I4I8))]
"TARGET_MMA"
- "<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
+ "<vvi4i4i8_insn> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
(define_insn "mma_<avvi4i4i8>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 6 "u8bit_cint_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 6 "u8bit_cint_operand" "n,n")]
MMA_AVVI4I4I8))]
"TARGET_MMA"
- "<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6"
+ "<avvi4i4i8_insn> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<vvi4i4i2>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "const_0_to_3_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "const_0_to_3_operand" "n,n")]
MMA_VVI4I4I2))]
"TARGET_MMA"
- "<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
+ "<vvi4i4i2_insn> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<avvi4i4i2>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 6 "const_0_to_3_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 6 "const_0_to_3_operand" "n,n")]
MMA_AVVI4I4I2))]
"TARGET_MMA"
- "<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
+ "<avvi4i4i2_insn> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<vvi4i4>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")]
MMA_VVI4I4))]
"TARGET_MMA"
- "<vvi4i4> %A0,%x1,%x2,%3,%4"
+ "<vvi4i4_insn> %A0,%x1,%x2,%3,%4"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<avvi4i4>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n")]
MMA_AVVI4I4))]
"TARGET_MMA"
- "<avvi4i4> %A0,%x2,%x3,%4,%5"
+ "<avvi4i4_insn> %A0,%x2,%x3,%4,%5"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<pvi4i2>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 4 "const_0_to_3_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 4 "const_0_to_3_operand" "n,n")]
MMA_PVI4I2))]
"TARGET_MMA"
- "<pvi4i2> %A0,%x1,%x2,%3,%4"
+ "<pvi4i2_insn> %A0,%x1,%x2,%3,%4"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<apvi4i2>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
- (match_operand:OO 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "const_0_to_3_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+ (match_operand:OO 2 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "const_0_to_3_operand" "n,n")]
MMA_APVI4I2))]
"TARGET_MMA"
- "<apvi4i2> %A0,%x2,%x3,%4,%5"
+ "<apvi4i2_insn> %A0,%x2,%x3,%4,%5"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<vvi4i4i4>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n")]
MMA_VVI4I4I4))]
"TARGET_MMA"
- "<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
+ "<vvi4i4i4_insn> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
+ (set_attr "prefixed" "yes")])
(define_insn "mma_<avvi4i4i4>"
- [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")
- (match_operand:SI 6 "const_0_to_15_operand" "n,n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n")
+ (match_operand:SI 6 "const_0_to_15_operand" "n,n")]
MMA_AVVI4I4I4))]
"TARGET_MMA"
- "<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
+ "<avvi4i4i4_insn> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")
- (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
+ (set_attr "prefixed" "yes")])
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index d1a42d7ea5e..52abd5e86e2 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -2348,6 +2348,7 @@ rs6000_debug_reg_global (void)
"wr reg_class = %s\n"
"wx reg_class = %s\n"
"wA reg_class = %s\n"
+ "wD reg_class = %s\n"
"\n",
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
@@ -2355,7 +2356,8 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wD]]);
nl = "\n";
for (m = 0; m < NUM_MACHINE_MODES; ++m)
@@ -3046,6 +3048,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_DIRECT_MOVE_128)
rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
+ /* Select which register set is used for MMA instructions. */
+ if (TARGET_MMA)
+ rs6000_constraints[RS6000_CONSTRAINT_wD]
+ = TARGET_DMF ? DMF_REGS : FLOAT_REGS;
+
/* Set up the reload helper and direct move functions. */
if (TARGET_VSX || TARGET_ALTIVEC)
{
@@ -13928,6 +13935,13 @@ print_operand (FILE *file, rtx x, int code)
fprintf (file, "%d", (REGNO (x) - FIRST_FPR_REGNO) / 4);
return;
+ case 'd':
+ /* If operand is a DMF accumulator, emit 'dm'. Otherwise don't emit
+ anything. */
+ if (REG_P (x) && DMF_REGNO_P (REGNO (x)))
+ fprintf (file, "dm");
+ return;
+
case 'D':
/* Like 'J' but get to the GT bit only. */
if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index d47337f7c51..8f2dd06a34a 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1220,6 +1220,7 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
+ RS6000_CONSTRAINT_wD, /* FPR_REGS if !DMF, DMR_REGS if DMF. */
RS6000_CONSTRAINT_MAX
};
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index d0a71ecbb80..264556c0f7e 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3267,6 +3267,12 @@ Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}.
@item wB
Signed 5-bit constant integer that can be loaded into an Altivec register.
+@item wD
+Register to use with MMA instructions or @code{NO_REGS}. If
+@option{-mdmf} is used, then this will be @code{FLOAT_REGS}. If
+@option{-mmma} is used but @option{-mdmf} is not used, then this will
+be @code{FLOAT_REGS}.
+
@item wE
Vector constant that can be loaded with the XXSPLTIB instruction.
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2022-10-14 17:35 [gcc(refs/users/meissner/heads/dmf001)] Make wD switch between FPRs and DMFs Michael Meissner
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