public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/dmf001)] Revert patch.
Date: Fri, 14 Oct 2022 18:23:23 +0000 (GMT) [thread overview]
Message-ID: <20221014182323.11D8A3856247@sourceware.org> (raw)
https://gcc.gnu.org/g:1a5cd271647e77f93253540d3f27142b63f16782
commit 1a5cd271647e77f93253540d3f27142b63f16782
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Oct 14 14:22:39 2022 -0400
Revert patch.
2022-10-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
* constraints.md (wD): Change wD to be FPR registers for power10 and DMF
registers for DMF systems.
* config/rs6000/mma.md (vvi4i4i8_insn): New int attribute.
(avvi4i4i8_insn): Likewise.
(vvi4i4i2_insn): Likewise.
(avvi4i4i2_insn): Likewise.
(vvi4i4_insn): Likewise.
(avvi4i4_insn): Likewise.
(pvi4i2_insn): Likewise.
(apvi4i2_insn): Likewise.
(vvi4i4i4_insn): Likewise.
(avvi4i4i4_insn): Likewise.
(mma_<vv>): Use wD constraint for accumulator inputs and outputs.
(mma_<avv>): Likewise.
(mma_<pv>): Likewise.
(mma_<apv>): Likewise.
(mma_<vvi4i4i8>): Likewise.
(mma_<avvi4i4i8>): Likewise.
(mma_<vvi4i4i2): Likewise.
(mma_<avvi4i4i2>): Likewise.
(mma_<vvi4i4>): Likewise.
(mma_<avvi4i4>): Likewise.
(mma_<pvi4i2>): Likewise.
(mma_<apvi4i2>): Likewise.
(mma_<vvi4i4i4): Likewise.
(mma_<avvi4i4i4>): Likewise.
* config/rs6000/s6000.cc (rs6000_debug_reg_global): Print what register
class wD implements.
(rs6000_init_hard_regno_mode_ok): Set up to make wD constraint choose
DMF accumualators on DMF systems and FPR registers on MMA systems
without DMF.
(print_operand): Add %d<n> output modifier, to print 'dm' or nothing to
switch MMA instructions being generated.
* config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wD option.
* doc/md.texi (PowerPC constraints): Document the wD constraint.
* ChangeLog.meissner: Revert.
Diff:
---
gcc/ChangeLog.meissner | 44 +------
gcc/config/rs6000/constraints.md | 4 +-
gcc/config/rs6000/mma.md | 256 ++++++++++++++++++---------------------
gcc/config/rs6000/rs6000.cc | 16 +--
gcc/config/rs6000/rs6000.h | 1 -
gcc/doc/md.texi | 6 -
6 files changed, 119 insertions(+), 208 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 11f48eb01fd..2016b4793a2 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,46 +1,4 @@
-==================== dmf001, patch #10
-
-Make wD switch between FPRs and DMFs.
-
-2022-10-14 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/
-
- * constraints.md (wD): Change wD to be FPR registers for power10 and DMF
- registers for DMF systems.
- * config/rs6000/mma.md (vvi4i4i8_insn): New int attribute.
- (avvi4i4i8_insn): Likewise.
- (vvi4i4i2_insn): Likewise.
- (avvi4i4i2_insn): Likewise.
- (vvi4i4_insn): Likewise.
- (avvi4i4_insn): Likewise.
- (pvi4i2_insn): Likewise.
- (apvi4i2_insn): Likewise.
- (vvi4i4i4_insn): Likewise.
- (avvi4i4i4_insn): Likewise.
- (mma_<vv>): Use wD constraint for accumulator inputs and outputs.
- (mma_<avv>): Likewise.
- (mma_<pv>): Likewise.
- (mma_<apv>): Likewise.
- (mma_<vvi4i4i8>): Likewise.
- (mma_<avvi4i4i8>): Likewise.
- (mma_<vvi4i4i2): Likewise.
- (mma_<avvi4i4i2>): Likewise.
- (mma_<vvi4i4>): Likewise.
- (mma_<avvi4i4>): Likewise.
- (mma_<pvi4i2>): Likewise.
- (mma_<apvi4i2>): Likewise.
- (mma_<vvi4i4i4): Likewise.
- (mma_<avvi4i4i4>): Likewise.
- * config/rs6000/s6000.cc (rs6000_debug_reg_global): Print what register
- class wD implements.
- (rs6000_init_hard_regno_mode_ok): Set up to make wD constraint choose
- DMF accumualators on DMF systems and FPR registers on MMA systems
- without DMF.
- (print_operand): Add %d<n> output modifier, to print 'dm' or nothing to
- switch MMA instructions being generated.
- * config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wD option.
- * doc/md.texi (PowerPC constraints): Document the wD constraint.
+==================== dmf001, patch #10, patch reverted.
==================== dmf001, patch #9
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 29bd7e021de..af1a0b2c563 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -107,8 +107,8 @@
(match_test "TARGET_P8_VECTOR")
(match_operand 0 "s5bit_cint_operand")))
-(define_register_constraint "wD" "rs6000_constraints[RS6000_CONSTRAINT_wD]"
- "Register class (FPR or DMF) to use for MMA instructions.")
+(define_register_constraint "wD" "DMF_REGS"
+ "DMF register.")
(define_constraint "wE"
"@internal Vector constant that can be loaded with the XXSPLTIB instruction."
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index fe6f9b692c0..c0ac6addac9 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -227,22 +227,13 @@
(define_int_attr vvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8 "pmxvi4ger8")])
-(define_int_attr vvi4i4i8_insn [(UNSPEC_MMA_PMXVI4GER8 "pm%d0xvi4ger8")])
-
(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP "pmxvi4ger8pp")])
-(define_int_attr avvi4i4i8_insn [(UNSPEC_MMA_PMXVI4GER8PP "pm%d0xvi4ger8pp")])
-
(define_int_attr vvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2 "pmxvi16ger2")
(UNSPEC_MMA_PMXVI16GER2S "pmxvi16ger2s")
(UNSPEC_MMA_PMXVF16GER2 "pmxvf16ger2")
(UNSPEC_MMA_PMXVBF16GER2 "pmxvbf16ger2")])
-(define_int_attr vvi4i4i2_insn [(UNSPEC_MMA_PMXVI16GER2 "pm%d0xvi16ger2")
- (UNSPEC_MMA_PMXVI16GER2S "pm%d0xvi16ger2s")
- (UNSPEC_MMA_PMXVF16GER2 "pm%d0xvf16ger2")
- (UNSPEC_MMA_PMXVBF16GER2 "pm%d0xvbf16ger2")])
-
(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP "pmxvi16ger2pp")
(UNSPEC_MMA_PMXVI16GER2SPP "pmxvi16ger2spp")
(UNSPEC_MMA_PMXVF16GER2PP "pmxvf16ger2pp")
@@ -254,55 +245,25 @@
(UNSPEC_MMA_PMXVBF16GER2NP "pmxvbf16ger2np")
(UNSPEC_MMA_PMXVBF16GER2NN "pmxvbf16ger2nn")])
-(define_int_attr avvi4i4i2_insn [(UNSPEC_MMA_PMXVI16GER2PP "pm%d0xvi16ger2pp")
- (UNSPEC_MMA_PMXVI16GER2SPP "pm%d0xvi16ger2spp")
- (UNSPEC_MMA_PMXVF16GER2PP "pm%d0xvf16ger2pp")
- (UNSPEC_MMA_PMXVF16GER2PN "pm%d0xvf16ger2pn")
- (UNSPEC_MMA_PMXVF16GER2NP "pm%d0xvf16ger2np")
- (UNSPEC_MMA_PMXVF16GER2NN "pm%d0xvf16ger2nn")
- (UNSPEC_MMA_PMXVBF16GER2PP "pm%d0xvbf16ger2pp")
- (UNSPEC_MMA_PMXVBF16GER2PN "pm%d0xvbf16ger2pn")
- (UNSPEC_MMA_PMXVBF16GER2NP "pm%d0xvbf16ger2np")
- (UNSPEC_MMA_PMXVBF16GER2NN "pm%d0xvbf16ger2nn")])
-
(define_int_attr vvi4i4 [(UNSPEC_MMA_PMXVF32GER "pmxvf32ger")])
-(define_int_attr vvi4i4_insn [(UNSPEC_MMA_PMXVF32GER "pm%d0xvf32ger")])
-
(define_int_attr avvi4i4 [(UNSPEC_MMA_PMXVF32GERPP "pmxvf32gerpp")
(UNSPEC_MMA_PMXVF32GERPN "pmxvf32gerpn")
(UNSPEC_MMA_PMXVF32GERNP "pmxvf32gernp")
(UNSPEC_MMA_PMXVF32GERNN "pmxvf32gernn")])
-(define_int_attr avvi4i4_insn [(UNSPEC_MMA_PMXVF32GERPP "pm%d0xvf32gerpp")
- (UNSPEC_MMA_PMXVF32GERPN "pm%d0xvf32gerpn")
- (UNSPEC_MMA_PMXVF32GERNP "pm%d0xvf32gernp")
- (UNSPEC_MMA_PMXVF32GERNN "pm%d0xvf32gernn")])
-
(define_int_attr pvi4i2 [(UNSPEC_MMA_PMXVF64GER "pmxvf64ger")])
-(define_int_attr pvi4i2_insn [(UNSPEC_MMA_PMXVF64GER "pm%d0xvf64ger")])
-
(define_int_attr apvi4i2 [(UNSPEC_MMA_PMXVF64GERPP "pmxvf64gerpp")
(UNSPEC_MMA_PMXVF64GERPN "pmxvf64gerpn")
(UNSPEC_MMA_PMXVF64GERNP "pmxvf64gernp")
(UNSPEC_MMA_PMXVF64GERNN "pmxvf64gernn")])
-(define_int_attr apvi4i2_insn [(UNSPEC_MMA_PMXVF64GERPP "pm%d0xvf64gerpp")
- (UNSPEC_MMA_PMXVF64GERPN "pm%d0xvf64gerpn")
- (UNSPEC_MMA_PMXVF64GERNP "pm%d0xvf64gernp")
- (UNSPEC_MMA_PMXVF64GERNN "pm%d0xvf64gernn")])
-
(define_int_attr vvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4 "pmxvi8ger4")])
-(define_int_attr vvi4i4i4_insn [(UNSPEC_MMA_PMXVI8GER4 "pm%d0xvi8ger4")])
-
(define_int_attr avvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4PP "pmxvi8ger4pp")
(UNSPEC_MMA_PMXVI8GER4SPP "pmxvi8ger4spp")])
-(define_int_attr avvi4i4i4_insn [(UNSPEC_MMA_PMXVI8GER4PP "pm%d0xvi8ger4pp")
- (UNSPEC_MMA_PMXVI8GER4SPP "pm%d0xvi8ger4spp")])
-
;; Vector pair support. OOmode can only live in VSRs.
(define_expand "movoo"
[(set (match_operand:OO 0 "nonimmediate_operand")
@@ -646,170 +607,183 @@
[(set_attr "type" "mma")])
(define_insn "mma_<vv>"
- [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")]
MMA_VV))]
"TARGET_MMA"
- "%d0<vv> %A0,%x1,%x2"
- [(set_attr "type" "mma")])
+ "<vv> %A0,%x1,%x2"
+ [(set_attr "type" "mma")
+ (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
(define_insn "mma_<avv>"
- [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")]
MMA_AVV))]
"TARGET_MMA"
- "%d0<avv> %A0,%x2,%x3"
- [(set_attr "type" "mma")])
+ "<avv> %A0,%x2,%x3"
+ [(set_attr "type" "mma")
+ (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
(define_insn "mma_<pv>"
- [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
- (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
+ (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")]
MMA_PV))]
"TARGET_MMA"
- "%d0<pv> %A0,%x1,%x2"
- [(set_attr "type" "mma")])
+ "<pv> %A0,%x1,%x2"
+ [(set_attr "type" "mma")
+ (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
(define_insn "mma_<apv>"
- [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
- (match_operand:OO 2 "vsx_register_operand" "v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
+ (match_operand:OO 2 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")]
MMA_APV))]
"TARGET_MMA"
- "%d0<apv> %A0,%x2,%x3"
- [(set_attr "type" "mma")])
+ "<apv> %A0,%x2,%x3"
+ [(set_attr "type" "mma")
+ (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
(define_insn "mma_<vvi4i4i8>"
- [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n")
- (match_operand:SI 5 "u8bit_cint_operand" "n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 5 "u8bit_cint_operand" "n,n,n")]
MMA_VVI4I4I8))]
"TARGET_MMA"
- "<vvi4i4i8_insn> %A0,%x1,%x2,%3,%4,%5"
+ "<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
(define_insn "mma_<avvi4i4i8>"
- [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n")
- (match_operand:SI 6 "u8bit_cint_operand" "n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 6 "u8bit_cint_operand" "n,n,n")]
MMA_AVVI4I4I8))]
"TARGET_MMA"
- "<avvi4i4i8_insn> %A0,%x2,%x3,%4,%5,%6"
+ "<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")])
+ (set_attr "prefixed" "yes")
+ (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
(define_insn "mma_<vvi4i4i2>"
- [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n")
- (match_operand:SI 5 "const_0_to_3_operand" "n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 5 "const_0_to_3_operand" "n,n,n")]
MMA_VVI4I4I2))]
"TARGET_MMA"
- "<vvi4i4i2_insn> %A0,%x1,%x2,%3,%4,%5"
+ "<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")])
+ (set_attr "prefixed" "yes")
+ (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
(define_insn "mma_<avvi4i4i2>"
- [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n")
- (match_operand:SI 6 "const_0_to_3_operand" "n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 6 "const_0_to_3_operand" "n,n,n")]
MMA_AVVI4I4I2))]
"TARGET_MMA"
- "<avvi4i4i2_insn> %A0,%x2,%x3,%4,%5,%6"
+ "<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")])
+ (set_attr "prefixed" "yes")
+ (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
(define_insn "mma_<vvi4i4>"
- [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")]
MMA_VVI4I4))]
"TARGET_MMA"
- "<vvi4i4_insn> %A0,%x1,%x2,%3,%4"
+ "<vvi4i4> %A0,%x1,%x2,%3,%4"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")])
+ (set_attr "prefixed" "yes")
+ (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
(define_insn "mma_<avvi4i4>"
- [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")]
MMA_AVVI4I4))]
"TARGET_MMA"
- "<avvi4i4_insn> %A0,%x2,%x3,%4,%5"
+ "<avvi4i4> %A0,%x2,%x3,%4,%5"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")])
+ (set_attr "prefixed" "yes")
+ (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
(define_insn "mma_<pvi4i2>"
- [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
- (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n")
- (match_operand:SI 4 "const_0_to_3_operand" "n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
+ (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 4 "const_0_to_3_operand" "n,n,n")]
MMA_PVI4I2))]
"TARGET_MMA"
- "<pvi4i2_insn> %A0,%x1,%x2,%3,%4"
+ "<pvi4i2> %A0,%x1,%x2,%3,%4"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")])
+ (set_attr "prefixed" "yes")
+ (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
(define_insn "mma_<apvi4i2>"
- [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
- (match_operand:OO 2 "vsx_register_operand" "v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n")
- (match_operand:SI 5 "const_0_to_3_operand" "n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
+ (match_operand:OO 2 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 5 "const_0_to_3_operand" "n,n,n")]
MMA_APVI4I2))]
"TARGET_MMA"
- "<apvi4i2_insn> %A0,%x2,%x3,%4,%5"
+ "<apvi4i2> %A0,%x2,%x3,%4,%5"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")])
+ (set_attr "prefixed" "yes")
+ (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
(define_insn "mma_<vvi4i4i4>"
- [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
- (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
- (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
- (match_operand:SI 3 "const_0_to_15_operand" "n,n")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
+ (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")]
MMA_VVI4I4I4))]
"TARGET_MMA"
- "<vvi4i4i4_insn> %A0,%x1,%x2,%3,%4,%5"
+ "<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")])
+ (set_attr "prefixed" "yes")
+ (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
(define_insn "mma_<avvi4i4i4>"
- [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
- (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
- (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
- (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
- (match_operand:SI 4 "const_0_to_15_operand" "n,n")
- (match_operand:SI 5 "const_0_to_15_operand" "n,n")
- (match_operand:SI 6 "const_0_to_15_operand" "n,n")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0,0")
+ (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")
+ (match_operand:SI 4 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 5 "const_0_to_15_operand" "n,n,n")
+ (match_operand:SI 6 "const_0_to_15_operand" "n,n,n")]
MMA_AVVI4I4I4))]
"TARGET_MMA"
- "<avvi4i4i4_insn> %A0,%x2,%x3,%4,%5,%6"
+ "<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
- (set_attr "prefixed" "yes")])
+ (set_attr "prefixed" "yes")
+ (set_attr "isa" "dmf,mma_fpr,mma_fpr")])
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 52abd5e86e2..d1a42d7ea5e 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -2348,7 +2348,6 @@ rs6000_debug_reg_global (void)
"wr reg_class = %s\n"
"wx reg_class = %s\n"
"wA reg_class = %s\n"
- "wD reg_class = %s\n"
"\n",
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
@@ -2356,8 +2355,7 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wD]]);
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
nl = "\n";
for (m = 0; m < NUM_MACHINE_MODES; ++m)
@@ -3048,11 +3046,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_DIRECT_MOVE_128)
rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
- /* Select which register set is used for MMA instructions. */
- if (TARGET_MMA)
- rs6000_constraints[RS6000_CONSTRAINT_wD]
- = TARGET_DMF ? DMF_REGS : FLOAT_REGS;
-
/* Set up the reload helper and direct move functions. */
if (TARGET_VSX || TARGET_ALTIVEC)
{
@@ -13935,13 +13928,6 @@ print_operand (FILE *file, rtx x, int code)
fprintf (file, "%d", (REGNO (x) - FIRST_FPR_REGNO) / 4);
return;
- case 'd':
- /* If operand is a DMF accumulator, emit 'dm'. Otherwise don't emit
- anything. */
- if (REG_P (x) && DMF_REGNO_P (REGNO (x)))
- fprintf (file, "dm");
- return;
-
case 'D':
/* Like 'J' but get to the GT bit only. */
if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 8f2dd06a34a..d47337f7c51 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1220,7 +1220,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
- RS6000_CONSTRAINT_wD, /* FPR_REGS if !DMF, DMR_REGS if DMF. */
RS6000_CONSTRAINT_MAX
};
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 264556c0f7e..d0a71ecbb80 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3267,12 +3267,6 @@ Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}.
@item wB
Signed 5-bit constant integer that can be loaded into an Altivec register.
-@item wD
-Register to use with MMA instructions or @code{NO_REGS}. If
-@option{-mdmf} is used, then this will be @code{FLOAT_REGS}. If
-@option{-mmma} is used but @option{-mdmf} is not used, then this will
-be @code{FLOAT_REGS}.
-
@item wE
Vector constant that can be loaded with the XXSPLTIB instruction.
next reply other threads:[~2022-10-14 18:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-14 18:23 Michael Meissner [this message]
2022-10-19 3:51 Michael Meissner
2022-10-20 4:14 Michael Meissner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221014182323.11D8A3856247@sourceware.org \
--to=meissner@gcc.gnu.org \
--cc=gcc-cvs@gcc.gnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).