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From: Kito Cheng <kito@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc r13-3448] RISC-V: Fix REG_CLASS_CONTENTS.
Date: Mon, 24 Oct 2022 02:21:33 +0000 (GMT)	[thread overview]
Message-ID: <20221024022133.34163385840A@sourceware.org> (raw)

https://gcc.gnu.org/g:65908ac84b840ded3331e000d303d0a5b4b426c8

commit r13-3448-g65908ac84b840ded3331e000d303d0a5b4b426c8
Author: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Date:   Mon Oct 24 09:39:16 2022 +0800

    RISC-V: Fix REG_CLASS_CONTENTS.
    
    Include V_REGS for ALL_REGS.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.h (REG_CLASS_CONTENTS): Fix ALL_REGS.

Diff:
---
 gcc/config/riscv/riscv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index acae68ebb2d..37363e975e1 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -516,7 +516,7 @@ enum reg_class
   { 0x00000000, 0x00000000, 0x00000000, 0x00000001 },	/* V0_REGS */		\
   { 0x00000000, 0x00000000, 0x00000000, 0xfffffffe },	/* VNoV0_REGS */	\
   { 0x00000000, 0x00000000, 0x00000000, 0xffffffff },	/* V_REGS */		\
-  { 0xffffffff, 0xffffffff, 0x00000003, 0x00000000 }	/* ALL_REGS */		\
+  { 0xffffffff, 0xffffffff, 0x0000000f, 0xffffffff }	/* ALL_REGS */		\
 }
 
 /* A C expression whose value is a register class containing hard

                 reply	other threads:[~2022-10-24  2:21 UTC|newest]

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