[gcc r13-3480] MIPS: add builtime option for -mcompact-branches

[gcc r13-3480] MIPS: add builtime option for -mcompact-branches

[YunQiang Su]

https://gcc.gnu.org/g:593632051f48a20bdc685d00d168f064d808bd7b

commit r13-3480-g593632051f48a20bdc685d00d168f064d808bd7b
Author: YunQiang Su <yunqiang.su@cipunited.com>
Date:   Sat May 8 05:45:54 2021 -0400

    MIPS: add builtime option for -mcompact-branches
    
    For R6+ target, it allows to configure gcc to use compact branches only
    if avaiable.
    
    gcc/ChangeLog:
            * config.gcc: add -with-compact-branches=policy build option.
            * doc/install.texi: Likewise.
            * config/mips/mips.h: Likewise.

Diff:
---
 gcc/config.gcc         | 13 +++++++++++--
 gcc/config/mips/mips.h |  3 ++-
 gcc/doc/install.texi   | 19 +++++++++++++++++++
 3 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 160c52c5429..52f9e988bf6 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4675,7 +4675,7 @@ case "${target}" in
 		;;
 
 	mips*-*-*)
-		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 madd4"
+		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 madd4 compact-branches"
 
 		case ${with_float} in
 		"" | soft | hard)
@@ -4828,6 +4828,15 @@ case "${target}" in
 			exit 1
 			;;
 		esac
+
+		case ${with_compact_branches} in
+		"" | never | always | optimal)
+			;;
+		*)
+			echo "Unknown compact-branches policy used in --with-compact-branches" 1>&2
+			exit 1
+			;;
+		esac
 		;;
 
 	loongarch*-*-*)
@@ -5772,7 +5781,7 @@ case ${target} in
 esac
 
 t=
-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4 isa_spec"
+all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4 isa_spec compact-branches"
 for option in $all_defaults
 do
 	eval "val=\$with_"`echo $option | sed s/-/_/g`
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index ed058b5db5f..69de74eb416 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -915,7 +915,8 @@ struct mips_cpu_info {
   {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
   {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" },			\
   {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \
-  {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" } \
+  {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" }, \
+  {"compact-branches", "%{!mcompact-branches=*:-mcompact-branches=%(VALUE)}" } \
 
 /* A spec that infers the:
    -mnan=2008 setting from a -mips argument,
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 4931e0b4fc5..c1876f24a84 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1543,6 +1543,25 @@ systems that support conditional traps).
 Division by zero checks use the break instruction.
 @end table
 
+@item --with-compact-branches=@var{policy}
+Specify how the compiler should generate branch instructions.
+This option is only supported on the MIPS target.
+The possibilities for @var{type} are:
+@table @code
+@item optimal
+Cause a delay slot branch to be used if one is available in the
+current ISA and the delay slot is successfully filled. If the delay slot
+is not filled, a compact branch will be chosen if one is available.
+@item never
+Ensures that compact branch instructions will never be generated.
+@item always
+Ensures that a compact branch instruction will be generated if available.
+If a compact branch instruction is not available,
+a delay slot form of the branch will be used instead.
+This option is supported from MIPS Release 6 onwards.
+For pre-R6/microMIPS/MIPS16, this option is just same as never/optimal.
+@end table
+
 @c If you make --with-llsc the default for additional targets,
 @c update the --with-llsc description in the MIPS section below.