[gcc(refs/users/meissner/heads/dmf001)] Make more changes to make DMF002 branch merge easier.

[gcc(refs/users/meissner/heads/dmf001)] Make more changes to make DMF002 branch merge easier.

[Michael Meissner]

https://gcc.gnu.org/g:4a423d9f852197481bf03c95bfe782f2dc5ae874

commit 4a423d9f852197481bf03c95bfe782f2dc5ae874
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Oct 27 01:14:27 2022 -0400

    Make more changes to make DMF002 branch merge easier.
    
    2022-10-27   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/constraints.md: Make various changes made in DMF002
            branch to make cherry picking changes easier.
            * config/rs6000/mma.md: Likewise.
            * config/rs6000/predicates.md: Likewise.
            * config/rs6000/rs6000.cc: Likewise.

Diff:
---
 gcc/config/rs6000/constraints.md |  2 +-
 gcc/config/rs6000/mma.md         |  3 ++-
 gcc/config/rs6000/predicates.md  |  2 +-
 gcc/config/rs6000/rs6000.cc      | 40 +++++++++++++++++-----------------------
 4 files changed, 21 insertions(+), 26 deletions(-)

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 5f10057a28a..809f117c1c4 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -108,7 +108,7 @@
        (match_operand 0 "s5bit_cint_operand")))
 
 (define_register_constraint "wD" "DM_REGS"
-  "Dense math register.")
+  "DMR register.")
 
 (define_constraint "wE"
   "@internal Vector constant that can be loaded with the XXSPLTIB instruction."
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 79fe19311d7..32b93e89e2e 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -543,7 +543,8 @@
   DONE;
 })
 
-;; On a system with dense math, we build the accumulators from two vector pairs.
+;; On a system with dense math, we build the accumulators from two vector
+;; pairs.
 
 (define_insn "mma_assemble_acc_dm"
  [(set (match_operand:XO 0 "dmr_operand" "=wD")
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 0ba02f1c15d..ede48189d3d 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -186,7 +186,7 @@
   return VLOGICAL_REGNO_P (REGNO (op));
 })
 
-;; Return 1 if op is a dense math register
+;; Return 1 if op is a DMR register
 (define_predicate "dmr_operand"
   (match_operand 0 "register_operand")
 {
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 9e7c88086a7..ef61ebc5fd9 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -291,7 +291,7 @@ enum rs6000_reg_type {
   FPR_REG_TYPE,
   SPR_REG_TYPE,
   CR_REG_TYPE,
-  DM_REG_TYPE
+  DMR_REG_TYPE
 };
 
 /* Map register class to register type.  */
@@ -340,17 +340,16 @@ static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
 /* Mask bits for each register class, indexed per mode.  Historically the
    compiler has been more restrictive which types can do PRE_MODIFY instead of
    PRE_INC and PRE_DEC, so keep track of sepaate bits for these two.  */
-typedef unsigned short addr_mask_type;
-
-#define RELOAD_REG_VALID	0x001	/* Mode valid in register..  */
-#define RELOAD_REG_MULTIPLE	0x002	/* Mode takes multiple registers.  */
-#define RELOAD_REG_INDEXED	0x004	/* Reg+reg addressing.  */
-#define RELOAD_REG_OFFSET	0x008	/* Reg+offset addressing. */
-#define RELOAD_REG_PRE_INCDEC	0x010	/* PRE_INC/PRE_DEC valid.  */
-#define RELOAD_REG_PRE_MODIFY	0x020	/* PRE_MODIFY valid.  */
-#define RELOAD_REG_AND_M16	0x040	/* AND -16 addressing.  */
-#define RELOAD_REG_QUAD_OFFSET	0x080	/* quad offset is limited.  */
-#define RELOAD_REG_NO_MEMORY	0x100	/* no memory access.  */
+typedef unsigned char addr_mask_type;
+
+#define RELOAD_REG_VALID	0x01	/* Mode valid in register..  */
+#define RELOAD_REG_MULTIPLE	0x02	/* Mode takes multiple registers.  */
+#define RELOAD_REG_INDEXED	0x04	/* Reg+reg addressing.  */
+#define RELOAD_REG_OFFSET	0x08	/* Reg+offset addressing. */
+#define RELOAD_REG_PRE_INCDEC	0x10	/* PRE_INC/PRE_DEC valid.  */
+#define RELOAD_REG_PRE_MODIFY	0x20	/* PRE_MODIFY valid.  */
+#define RELOAD_REG_AND_M16	0x40	/* AND -16 addressing.  */
+#define RELOAD_REG_QUAD_OFFSET	0x80	/* quad offset is limited.  */
 
 /* Register type masks based on the type, of valid addressing modes.  */
 struct rs6000_reg_addr {
@@ -2168,7 +2167,7 @@ rs6000_debug_vector_unit (enum rs6000_vector v)
 DEBUG_FUNCTION char *
 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
 {
-  static char ret[10];
+  static char ret[8];
   char *p = ret;
 
   if ((mask & RELOAD_REG_VALID) != 0)
@@ -2208,11 +2207,6 @@ rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
   else if (keep_spaces)
     *p++ = ' ';
 
-  if ((mask & RELOAD_REG_NO_MEMORY) != 0)
-    *p++ = 'M';
-  else if (keep_spaces)
-    *p++ = ' ';
-
   *p = '\0';
 
   return ret;
@@ -2684,7 +2678,7 @@ rs6000_setup_reg_addr_masks (void)
 	    {
 	      if (TARGET_DENSE_MATH && (m2 == XOmode || m2 == TDOmode))
 		{
-		  addr_mask = RELOAD_REG_VALID | RELOAD_REG_NO_MEMORY;
+		  addr_mask = RELOAD_REG_VALID;
 		  reg_addr[m].addr_mask[rc] = addr_mask;
 		  any_addr_mask |= addr_mask;
 		}
@@ -2871,7 +2865,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
   reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
   reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
   reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
-  reg_class_to_reg_type[(int)DM_REGS] = DM_REG_TYPE;
+  reg_class_to_reg_type[(int)DM_REGS] = DMR_REG_TYPE;
 
   if (TARGET_VSX)
     {
@@ -12520,8 +12514,8 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
   /* We can transfer between VSX registers and DMR registers without needing
      extra registers.  */
   if (TARGET_DENSE_MATH && (mode == XOmode || mode == TDOmode)
-      && ((to_type == DM_REG_TYPE && from_type == VSX_REG_TYPE)
-	  || (to_type == VSX_REG_TYPE && from_type == DM_REG_TYPE)))
+      && ((to_type == DMR_REG_TYPE && from_type == VSX_REG_TYPE)
+	  || (to_type == VSX_REG_TYPE && from_type == DMR_REG_TYPE)))
     return true;
 
   return false;
@@ -24118,7 +24112,7 @@ rs6000_debugger_regno (unsigned int regno, unsigned int format)
   if (regno == 64)
     return 64;
   /* XXX: This is a guess.  The GCC register number for FIRST_DMR_REGNO is 111,
-     but the frame pointer regnum above uses that.  */
+     but the frame pointer regnum uses that.  */
   if (DMR_REGNO_P (regno))
     return regno - FIRST_DMR_REGNO + 112;