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* [gcc(refs/users/meissner/heads/dmf002)] Make wD match either FLOAT_REGS or DM_REGS.
@ 2022-11-03 2:12 Michael Meissner
0 siblings, 0 replies; only message in thread
From: Michael Meissner @ 2022-11-03 2:12 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ba5e4e4c7e70b417eb82f118613aa8dd83f1c2cf
commit ba5e4e4c7e70b417eb82f118613aa8dd83f1c2cf
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Nov 2 22:12:30 2022 -0400
Make wD match either FLOAT_REGS or DM_REGS.
2022-11-02 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/constraint.md (wD): Match FLOAT_REGS on power10, DM_REGS
if dense math.
* config/rs6000/rs6000.md (rs6000_debug_reg_global): For -mdebug=reg,
print the register class for wD.
(rs6000_init_hard_regno_mode_ok): Set the register class for wD.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): New enumaation
value for wD.
* doc/md.texi (PowerPC constraints): Document wD constraint.
Diff:
---
gcc/config/rs6000/constraints.md | 4 ++--
gcc/config/rs6000/rs6000.cc | 11 ++++++++++-
gcc/config/rs6000/rs6000.h | 1 +
gcc/doc/md.texi | 3 +++
4 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 809f117c1c4..82856b8e8c2 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -107,8 +107,8 @@
(match_test "TARGET_P8_VECTOR")
(match_operand 0 "s5bit_cint_operand")))
-(define_register_constraint "wD" "DM_REGS"
- "DMR register.")
+(define_register_constraint "wD" "rs6000_constraints[RS6000_CONSTRAINT_wD]"
+ "Accumulator register.")
(define_constraint "wE"
"@internal Vector constant that can be loaded with the XXSPLTIB instruction."
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 901ae345ce5..b37110841c6 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -2369,6 +2369,7 @@ rs6000_debug_reg_global (void)
"wr reg_class = %s\n"
"wx reg_class = %s\n"
"wA reg_class = %s\n"
+ "wD reg_class = %s\n"
"\n",
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
@@ -2376,7 +2377,8 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wD]]);
nl = "\n";
for (m = 0; m < NUM_MACHINE_MODES; ++m)
@@ -3060,6 +3062,13 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_DIRECT_MOVE_128)
rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
+ /* Support for the accumulator registers, either FPR registers (aka original
+ mma) or DMR registers (dense math). */
+ if (TARGET_DENSE_MATH)
+ rs6000_constraints[RS6000_CONSTRAINT_wD] = DM_REGS;
+ else if (TARGET_MMA)
+ rs6000_constraints[RS6000_CONSTRAINT_wD] = FLOAT_REGS;
+
/* Set up the reload helper and direct move functions. */
if (TARGET_VSX || TARGET_ALTIVEC)
{
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 5d38257ebff..dd132a5945e 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1221,6 +1221,7 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
+ RS6000_CONSTRAINT_wD, /* Accumulator regs if MMA/Dense Math. */
RS6000_CONSTRAINT_MAX
};
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index d0a71ecbb80..65ccb1de667 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3264,6 +3264,9 @@ Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise, @code{NO_REGS}.
@item wA
Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}.
+@item wD
+Accumulator register for either @option{-mma} or @option{-mdense-math}.
+
@item wB
Signed 5-bit constant integer that can be loaded into an Altivec register.
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