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* [gcc(refs/users/meissner/heads/dmf003)] Add LAGEN and PLAGEN support.
@ 2022-11-04 7:51 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2022-11-04 7:51 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:98fe98cac5cfdd5b38969635bdd1d178fb1d1ed1
commit 98fe98cac5cfdd5b38969635bdd1d178fb1d1ed1
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Nov 4 03:51:10 2022 -0400
Add LAGEN and PLAGEN support.
2022-11-04 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mlagen.
* config/rs6000/rs6000.cc (rs6000_file_start): Add macros for fake lagen
and plagen instructions.
(rs6000_opt_masks): Add -mlagen.
* config/rs6000/rs6000.md (lagendi3): New insn for -mlagen.
(plagendi3_nora): Likewise.
(plagendi3): Likewise.
(plagendi3_noshift): Likewise.
* config/rs6000/rs6000.opt (-mlagen): New option.
Diff:
---
gcc/ChangeLog.meissner | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 313ab34ee01..47eef9fce7b 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,22 @@
-==================== Dmf003 branch, patch #1.
+==================== Dmf003 branch, patch #5.
+
+Add LAGEN and PLAGEN support.
+
+2022-10-27 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mlagen.
+ * config/rs6000/rs6000.cc (rs6000_file_start): Add macros for fake lagen
+ and plagen instructions.
+ (rs6000_opt_masks): Add -mlagen.
+ * config/rs6000/rs6000.md (lagendi3): New insn for -mlagen.
+ (plagendi3_nora): Likewise.
+ (plagendi3): Likewise.
+ (plagendi3_noshift): Likewise.
+ * config/rs6000/rs6000.opt (-mlagen): New option.
+
+==================== Dmf003 branch, patch #4.
Add support for 1,024 bit DMR registers.
@@ -49,7 +67,7 @@ gcc/
(dmr_type_node): Likewise.
(ptr_dmr_type_node): Likewise.
-==================== Dmf003 branch, patch #1.
+==================== Dmf003 branch, patch #3.
Switch to dense math names for all MMA operations.
@@ -83,7 +101,7 @@ gcc/
(mma_<vvi4i4i4>): Likewise.
(mma_<avvi4i4i4>): Likewise.
-==================== Dmf003 branch, patch #1.
+==================== Dmf003 branch, patch #2.
Add support for accumulators in DMR registers.
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/dmf003)] Add LAGEN and PLAGEN support.
@ 2022-11-04 7:49 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2022-11-04 7:49 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ce130172d436fe507fec430722da824349533b67
commit ce130172d436fe507fec430722da824349533b67
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Nov 4 03:49:29 2022 -0400
Add LAGEN and PLAGEN support.
2022-11-04 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mlagen.
* config/rs6000/rs6000.cc (rs6000_file_start): Add macros for fake lagen
and plagen instructions.
(rs6000_opt_masks): Add -mlagen.
* config/rs6000/rs6000.md (lagendi3): New insn for -mlagen.
(plagendi3_nora): Likewise.
(plagendi3): Likewise.
(plagendi3_noshift): Likewise.
* config/rs6000/rs6000.opt (-mlagen): New option.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 1 +
gcc/config/rs6000/rs6000.cc | 15 ++++++++++++++
gcc/config/rs6000/rs6000.md | 42 +++++++++++++++++++++++++++++++++++++++
gcc/config/rs6000/rs6000.opt | 4 ++++
4 files changed, 62 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 952e9447e20..4628955f80a 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -139,6 +139,7 @@
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND \
+ | OPTION_MASK_LAGEN \
| OPTION_MASK_POWER10 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_FUTURE \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index a8ec5540caf..2b920f3dfed 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -6098,6 +6098,20 @@ rs6000_file_start (void)
if (DEFAULT_ABI == ABI_ELFv2)
fprintf (file, "\t.abiversion 2\n");
+
+ if (TARGET_LAGEN)
+ {
+ fprintf (file, "\n");
+ fprintf (file, "\t.macro lagen rt,ra,rb,n\n");
+ fprintf (file, "\taddi \\rt,\\rt,0\n");
+ fprintf (file, "\t.endm\n");
+ fprintf (file, "\n");
+
+ fprintf (file, "\t.macro plagen rt,d,rb,n\n");
+ fprintf (file, "\tpaddi \\rt,\\rt,0\n");
+ fprintf (file, "\t.endm\n");
+ fprintf (file, "\n");
+ }
}
\f
@@ -24334,6 +24348,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "hard-dfp", OPTION_MASK_DFP, false, true },
{ "htm", OPTION_MASK_HTM, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
+ { "lagen", OPTION_MASK_LAGEN, false, true },
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
{ "mfpgpr", 0, false, true },
{ "mma", OPTION_MASK_MMA, false, true },
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 709a75cb542..78f427aa950 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -15580,6 +15580,48 @@
}
[(set_attr "type" "load")])
\f
+;; RFC 2679, Scaled index address generation
+(define_insn "*lagendi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (plus:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand 2 "u5bit_cint_operand" "n"))
+ (match_operand:DI 3 "base_reg_operand" "b")))]
+ "TARGET_LAGEN"
+ "lagen %0,%3,%1,%2"
+ [(set_attr "type" "shift")])
+
+(define_insn "*plagendi3_nora"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (plus:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand 2 "u5bit_cint_operand" "n"))
+ (match_operand 3 "s32bit_cint_operand" "n")))]
+ "TARGET_LAGEN && TARGET_PREFIXED"
+ "plagen %0,%3(0),%1,%2"
+ [(set_attr "type" "shift")
+ (set_attr "prefixed" "yes")])
+
+(define_insn "*plagendi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (plus:DI (plus:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand 2 "u5bit_cint_operand" "n"))
+ (match_operand:DI 3 "base_reg_operand" "b"))
+ (match_operand 4 "s32bit_cint_operand" "n")))]
+ "TARGET_LAGEN && TARGET_PREFIXED"
+ "plagen %0,%4(%3),%1,%2"
+ [(set_attr "type" "shift")
+ (set_attr "prefixed" "yes")])
+
+(define_insn "*plagendi3_noshift"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (plus:DI (plus:DI (match_operand:DI 1 "base_reg_operand" "b")
+ (match_operand:DI 2 "gpc_reg_operand" "r"))
+ (match_operand 3 "s32bit_cint_operand" "n")))]
+ "TARGET_LAGEN && TARGET_PREFIXED"
+ "plagen %0,%3(%1),%2,0"
+ [(set_attr "type" "shift")
+ (set_attr "prefixed" "yes")])
+
+\f
(include "sync.md")
(include "vector.md")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 3681d089368..50cf342b25c 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -628,6 +628,10 @@ mdense-math
Target Undocumented Mask(DENSE_MATH) Var(rs6000_isa_flags)
Generate (do not generate) dense math instructions.
+mlagen
+Target Undocumented Mask(LAGEN) Var(rs6000_isa_flags)
+Generate (do not generate) LAGEN instructions.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
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2022-11-04 7:49 Michael Meissner
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