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From: Philipp Tomsich <ptomsich@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-3878] RISC-V: Fix selection of pipeline model for sifive-7-series Date: Thu, 10 Nov 2022 13:57:52 +0000 (GMT) [thread overview] Message-ID: <20221110135753.882DC3858D20@sourceware.org> (raw) https://gcc.gnu.org/g:2f6cb9c51a933de19cd88f4c9180ac9cf5093522 commit r13-3878-g2f6cb9c51a933de19cd88f4c9180ac9cf5093522 Author: Philipp Tomsich <philipp.tomsich@vrull.eu> Date: Thu Nov 10 00:43:05 2022 +0100 RISC-V: Fix selection of pipeline model for sifive-7-series A few of the gcc.target/riscv/mcpu-*.c tests have been failing for a while now, due to the pipeline model for sifive-7-series not being selected despite -mtune=sifive-7-series. The root cause is that the respective RISCV_TUNE entry points to generic instead. Fix this. Fixes 97d1ed67fc6 ("RISC-V: Support --target-help for -mcpu/-mtune") gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): Update sifive-7-series to point to the sifive_7 pipeline description. Diff: --- gcc/config/riscv/riscv-cores.def | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index b84ad999ac1..31ad34682c5 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -36,7 +36,7 @@ RISCV_TUNE("rocket", generic, rocket_tune_info) RISCV_TUNE("sifive-3-series", generic, rocket_tune_info) RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) -RISCV_TUNE("sifive-7-series", generic, sifive_7_tune_info) +RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) RISCV_TUNE("size", generic, optimize_size_tune_info)
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