[gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:54a8598f5fe52994965538eea71407b9ad5a686c

commit 54a8598f5fe52994965538eea71407b9ad5a686c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Nov 11 22:48:59 2022 -0500

    Update ChangeLog.meissner.
    
    2022-11-11   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 39 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 37 insertions(+), 2 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index c910d1b5625..3fa2264624b 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,6 +1,40 @@
+==================== Dmf004 branch, patch #17.
+
+Support load/store vector with right length.
+
+This patch adds support for new instructions that may be added to the PowerPC
+architecture in the future to enhance the load and store vector with length
+instructions.
+
+The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use
+since the count for the number of bytes must be in the top 8 bits of the GPR
+register, instead of the bottom 8 bits.  This meant that code generating these
+instructions typically had to do a shift left by 56 bits to get the count into
+the right position.  In a future version of the PowerPC architecture, new
+variants of these instructions might be added that expect the count to be in
+the bottom 8 bits of the GPR register.  These patches add this support to GCC
+if the user uses the -mcpu=future option.
+
+2022-11-11   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl with
+	the shift count automaticaly used in the insn.
+	(lxvrl): New insn for -mcpu=future.
+	(lxvrll): Likewise.
+	(stxvl): If -mcpu=future, generate the stxvl with the shift count
+	automaticaly used in the insn.
+	(stxvrl): New insn for -mcpu=future.
+	(stxvrll): Likewise.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/lxvrl.c: New test.
+
 ==================== Dmf004 branch, patch #16.
 
-Add saturating subtract built-in.
+Add saturating subtract built-ins.
 
 This patch adds support for a saturating subtract built-in function that may be
 added to a future PowerPC processor.  Note, if it is added, the name of the
@@ -32,12 +66,13 @@ gcc/
 	built-in insn declarations.
 	(sat_sub<mode>3_dot): Likewise.
 	(sat_sub<mode>3_dot2): Likewise.
+	* doc/extend.texi (Future PowerPC built-ins): New section.
 
 gcc/testsuite/
 
 	* gcc.target/powerpc/subfus-1.c: New test.
 	* gcc.target/powerpc/subfus-2.c: Likewise.
-	* lib/target-supports.exp (check_effective_target_powerpc_subfus_ok):
+	* lib/target-supports.exp (check_effective_target_powerpc_future_ok):
 	New effective target.
 
 ==================== Dmf004 branch, patch #15.