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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner. Date: Thu, 17 Nov 2022 21:54:04 +0000 (GMT) [thread overview] Message-ID: <20221117215404.BD2B4384F6C6@sourceware.org> (raw) https://gcc.gnu.org/g:7c6a0007d3c4a1764647cf35019c1541d5b9c36d commit 7c6a0007d3c4a1764647cf35019c1541d5b9c36d Author: Michael Meissner <meissner@linux.ibm.com> Date: Fri Nov 11 22:48:59 2022 -0500 Update ChangeLog.meissner. 2022-11-11 Michael Meissner <meissner@linux.ibm.com> gcc/ * ChangeLog.meissner: Update. Diff: --- gcc/ChangeLog.meissner | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index c910d1b5625..3fa2264624b 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,6 +1,40 @@ +==================== Dmf004 branch, patch #17. + +Support load/store vector with right length. + +This patch adds support for new instructions that may be added to the PowerPC +architecture in the future to enhance the load and store vector with length +instructions. + +The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use +since the count for the number of bytes must be in the top 8 bits of the GPR +register, instead of the bottom 8 bits. This meant that code generating these +instructions typically had to do a shift left by 56 bits to get the count into +the right position. In a future version of the PowerPC architecture, new +variants of these instructions might be added that expect the count to be in +the bottom 8 bits of the GPR register. These patches add this support to GCC +if the user uses the -mcpu=future option. + +2022-11-11 Michael Meissner <meissner@linux.ibm.com> + +gcc/ + + * config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl with + the shift count automaticaly used in the insn. + (lxvrl): New insn for -mcpu=future. + (lxvrll): Likewise. + (stxvl): If -mcpu=future, generate the stxvl with the shift count + automaticaly used in the insn. + (stxvrl): New insn for -mcpu=future. + (stxvrll): Likewise. + +gcc/testsuite/ + + * gcc.target/powerpc/lxvrl.c: New test. + ==================== Dmf004 branch, patch #16. -Add saturating subtract built-in. +Add saturating subtract built-ins. This patch adds support for a saturating subtract built-in function that may be added to a future PowerPC processor. Note, if it is added, the name of the @@ -32,12 +66,13 @@ gcc/ built-in insn declarations. (sat_sub<mode>3_dot): Likewise. (sat_sub<mode>3_dot2): Likewise. + * doc/extend.texi (Future PowerPC built-ins): New section. gcc/testsuite/ * gcc.target/powerpc/subfus-1.c: New test. * gcc.target/powerpc/subfus-2.c: Likewise. - * lib/target-supports.exp (check_effective_target_powerpc_subfus_ok): + * lib/target-supports.exp (check_effective_target_powerpc_future_ok): New effective target. ==================== Dmf004 branch, patch #15.
next reply other threads:[~2022-11-17 21:54 UTC|newest] Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-17 21:54 Michael Meissner [this message] -- strict thread matches above, loose matches on Subject: below -- 2022-11-17 22:32 Michael Meissner 2022-11-17 21:56 Michael Meissner 2022-11-17 21:55 Michael Meissner 2022-11-17 21:55 Michael Meissner 2022-11-17 21:55 Michael Meissner 2022-11-17 21:55 Michael Meissner 2022-11-17 21:55 Michael Meissner 2022-11-17 21:55 Michael Meissner 2022-11-17 21:54 Michael Meissner 2022-11-17 21:54 Michael Meissner 2022-11-17 21:54 Michael Meissner 2022-11-17 21:53 Michael Meissner 2022-11-17 21:53 Michael Meissner 2022-11-17 21:52 Michael Meissner 2022-11-17 20:06 Michael Meissner 2022-11-17 5:15 Michael Meissner 2022-11-16 20:57 Michael Meissner 2022-11-16 18:55 Michael Meissner 2022-11-16 18:12 Michael Meissner 2022-11-16 8:30 Michael Meissner 2022-11-15 21:24 Michael Meissner 2022-11-15 18:55 Michael Meissner 2022-11-15 17:29 Michael Meissner 2022-11-15 1:00 Michael Meissner 2022-11-12 3:49 Michael Meissner 2022-11-11 23:16 Michael Meissner 2022-11-09 22:40 Michael Meissner 2022-11-09 5:58 Michael Meissner
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