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* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: No extensions for SImode min/max against safe constant
@ 2022-11-15 14:00 Philipp Tomsich
0 siblings, 0 replies; 4+ messages in thread
From: Philipp Tomsich @ 2022-11-15 14:00 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:37db290428213b7ce14fb838262af7675aac20ae
commit 37db290428213b7ce14fb838262af7675aac20ae
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Sun Oct 16 10:51:47 2022 +0200
RISC-V: No extensions for SImode min/max against safe constant
Optimize the common case of a SImode min/max against a constant
that is safe both for sign- and zero-extension.
E.g., consider the case
int f(unsigned int* a)
{
const int C = 1000;
return *a * 3 > C ? C : *a * 3;
}
where the constant C will yield the same result in DImode whether
sign- or zero-extended.
This should eventually go away once the lowering to RTL smartens up
and considers the precision/signedness and the value-ranges of the
operands to MIN_EXPR nad MAX_EXPR.
gcc/ChangeLog:
* config/riscv/bitmanip.md (*minmax): Additional pattern for
min/max against constants that are extension-invariant.
* config/riscv/iterators.md (minmax_optab): Add an iterator
that has only min and max rtl.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-min-max-02.c: New test.
Series-version: 2
Series-changes: 2
- fixes the use minmax_optab (was: bitmanip_optab), which didn't get
applied to the cherry-pick on the previous submission
Series-to: gcc-patches@gcc.gnu.org
Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
Series-cc: Vineet Gupta <vineetg@rivosinc.com>
Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
Series-cc: Kito Cheng <kito.cheng@gmail.com>
Series-cc: Jeff Law <jlaw@ventanamicro.com>
Diff:
---
gcc/config/riscv/bitmanip.md | 18 ++++++++++++++++++
gcc/config/riscv/iterators.md | 4 ++++
gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c | 14 ++++++++++++++
3 files changed, 36 insertions(+)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index a545cd3f82b..8b6a7cad3f6 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -368,6 +368,24 @@
"<bitmanip_insn>\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
+;; Optimize the common case of a SImode min/max against a constant
+;; that is safe both for sign- and zero-extension.
+(define_insn_and_split "*minmax"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extend:DI
+ (subreg:SI
+ (bitmanip_minmax:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
+ (match_operand:DI 2 "immediate_operand" "i"))
+ 0)))
+ (clobber (match_scratch:DI 3 "=&r"))
+ (clobber (match_scratch:DI 4 "=&r"))]
+ "TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
+ (set (match_dup 4) (match_dup 2))
+ (set (match_dup 0) (<minmax_optab>:DI (match_dup 3) (match_dup 4)))])
+
;; ZBS extension.
(define_insn "*bset<mode>"
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 50380ecfac9..cbbf61f6514 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -213,6 +213,10 @@
[(plus "add") (ior "or") (xor "xor") (and "and")])
; bitmanip code attributes
+(define_code_attr minmax_optab [(smin "smin")
+ (smax "smax")
+ (umin "umin")
+ (umax "umax")])
(define_code_attr bitmanip_optab [(smin "smin")
(smax "smax")
(umin "umin")
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c
new file mode 100644
index 00000000000..b462859f10f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba_zbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */
+
+int f(unsigned int* a)
+{
+ const int C = 1000;
+ return *a * 3 > C ? C : *a * 3;
+}
+
+/* { dg-final { scan-assembler-times "minu" 1 } } */
+/* { dg-final { scan-assembler-times "sext.w" 1 } } */
+/* { dg-final { scan-assembler-not "zext.w" } } */
+
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: No extensions for SImode min/max against safe constant
@ 2022-11-18 20:22 Philipp Tomsich
0 siblings, 0 replies; 4+ messages in thread
From: Philipp Tomsich @ 2022-11-18 20:22 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8471d7eb4e63a61c77fc96a2f81800a90ff1cb20
commit 8471d7eb4e63a61c77fc96a2f81800a90ff1cb20
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Sun Oct 16 10:51:47 2022 +0200
RISC-V: No extensions for SImode min/max against safe constant
Optimize the common case of a SImode min/max against a constant
that is safe both for sign- and zero-extension.
E.g., consider the case
int f(unsigned int* a)
{
const int C = 1000;
return *a * 3 > C ? C : *a * 3;
}
where the constant C will yield the same result in DImode whether
sign- or zero-extended.
This should eventually go away once the lowering to RTL smartens up
and considers the precision/signedness and the value-ranges of the
operands to MIN_EXPR nad MAX_EXPR.
gcc/ChangeLog:
* config/riscv/bitmanip.md (*minmax): Additional pattern for
min/max against constants that are extension-invariant.
* config/riscv/iterators.md (minmax_optab): Add an iterator
that has only min and max rtl.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-min-max-02.c: New test.
Series-version: 2
Series-changes: 2
- fixes the use minmax_optab (was: bitmanip_optab), which didn't get
applied to the cherry-pick on the previous submission
Series-to: gcc-patches@gcc.gnu.org
Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
Series-cc: Vineet Gupta <vineetg@rivosinc.com>
Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
Series-cc: Kito Cheng <kito.cheng@gmail.com>
Series-cc: Jeff Law <jlaw@ventanamicro.com>
Diff:
---
gcc/config/riscv/bitmanip.md | 18 ++++++++++++++++++
gcc/config/riscv/iterators.md | 4 ++++
gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c | 14 ++++++++++++++
3 files changed, 36 insertions(+)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 58bac7231e3..d17133d58c1 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -368,6 +368,24 @@
"<bitmanip_insn>\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
+;; Optimize the common case of a SImode min/max against a constant
+;; that is safe both for sign- and zero-extension.
+(define_insn_and_split "*minmax"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extend:DI
+ (subreg:SI
+ (bitmanip_minmax:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
+ (match_operand:DI 2 "immediate_operand" "i"))
+ 0)))
+ (clobber (match_scratch:DI 3 "=&r"))
+ (clobber (match_scratch:DI 4 "=&r"))]
+ "TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
+ (set (match_dup 4) (match_dup 2))
+ (set (match_dup 0) (<minmax_optab>:DI (match_dup 3) (match_dup 4)))])
+
;; ZBS extension.
(define_insn "*bset<mode>"
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index ab1f4ee8d34..efdd3ccc9a7 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -221,6 +221,10 @@
[(plus "add") (ior "or") (xor "xor") (and "and")])
; bitmanip code attributes
+(define_code_attr minmax_optab [(smin "smin")
+ (smax "smax")
+ (umin "umin")
+ (umax "umax")])
(define_code_attr bitmanip_optab [(smin "smin")
(smax "smax")
(umin "umin")
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c
new file mode 100644
index 00000000000..b462859f10f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba_zbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */
+
+int f(unsigned int* a)
+{
+ const int C = 1000;
+ return *a * 3 > C ? C : *a * 3;
+}
+
+/* { dg-final { scan-assembler-times "minu" 1 } } */
+/* { dg-final { scan-assembler-times "sext.w" 1 } } */
+/* { dg-final { scan-assembler-not "zext.w" } } */
+
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: No extensions for SImode min/max against safe constant
@ 2022-11-18 11:34 Philipp Tomsich
0 siblings, 0 replies; 4+ messages in thread
From: Philipp Tomsich @ 2022-11-18 11:34 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a34c0e981a8df401b1a92a600aeef358d4f5748f
commit a34c0e981a8df401b1a92a600aeef358d4f5748f
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Sun Oct 16 10:51:47 2022 +0200
RISC-V: No extensions for SImode min/max against safe constant
Optimize the common case of a SImode min/max against a constant
that is safe both for sign- and zero-extension.
E.g., consider the case
int f(unsigned int* a)
{
const int C = 1000;
return *a * 3 > C ? C : *a * 3;
}
where the constant C will yield the same result in DImode whether
sign- or zero-extended.
This should eventually go away once the lowering to RTL smartens up
and considers the precision/signedness and the value-ranges of the
operands to MIN_EXPR nad MAX_EXPR.
gcc/ChangeLog:
* config/riscv/bitmanip.md (*minmax): Additional pattern for
min/max against constants that are extension-invariant.
* config/riscv/iterators.md (minmax_optab): Add an iterator
that has only min and max rtl.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-min-max-02.c: New test.
Series-version: 2
Series-changes: 2
- fixes the use minmax_optab (was: bitmanip_optab), which didn't get
applied to the cherry-pick on the previous submission
Series-to: gcc-patches@gcc.gnu.org
Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
Series-cc: Vineet Gupta <vineetg@rivosinc.com>
Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
Series-cc: Kito Cheng <kito.cheng@gmail.com>
Series-cc: Jeff Law <jlaw@ventanamicro.com>
Diff:
---
gcc/config/riscv/bitmanip.md | 18 ++++++++++++++++++
gcc/config/riscv/iterators.md | 4 ++++
gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c | 14 ++++++++++++++
3 files changed, 36 insertions(+)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 2f89fd6aee1..db16f83b46e 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -368,6 +368,24 @@
"<bitmanip_insn>\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
+;; Optimize the common case of a SImode min/max against a constant
+;; that is safe both for sign- and zero-extension.
+(define_insn_and_split "*minmax"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extend:DI
+ (subreg:SI
+ (bitmanip_minmax:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
+ (match_operand:DI 2 "immediate_operand" "i"))
+ 0)))
+ (clobber (match_scratch:DI 3 "=&r"))
+ (clobber (match_scratch:DI 4 "=&r"))]
+ "TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
+ (set (match_dup 4) (match_dup 2))
+ (set (match_dup 0) (<minmax_optab>:DI (match_dup 3) (match_dup 4)))])
+
;; ZBS extension.
(define_insn "*bset<mode>"
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 50380ecfac9..cbbf61f6514 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -213,6 +213,10 @@
[(plus "add") (ior "or") (xor "xor") (and "and")])
; bitmanip code attributes
+(define_code_attr minmax_optab [(smin "smin")
+ (smax "smax")
+ (umin "umin")
+ (umax "umax")])
(define_code_attr bitmanip_optab [(smin "smin")
(smax "smax")
(umin "umin")
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c
new file mode 100644
index 00000000000..b462859f10f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba_zbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */
+
+int f(unsigned int* a)
+{
+ const int C = 1000;
+ return *a * 3 > C ? C : *a * 3;
+}
+
+/* { dg-final { scan-assembler-times "minu" 1 } } */
+/* { dg-final { scan-assembler-times "sext.w" 1 } } */
+/* { dg-final { scan-assembler-not "zext.w" } } */
+
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: No extensions for SImode min/max against safe constant
@ 2022-11-17 22:25 Philipp Tomsich
0 siblings, 0 replies; 4+ messages in thread
From: Philipp Tomsich @ 2022-11-17 22:25 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:19d866f58a318439a7ab69075b0a375b23248806
commit 19d866f58a318439a7ab69075b0a375b23248806
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Sun Oct 16 10:51:47 2022 +0200
RISC-V: No extensions for SImode min/max against safe constant
Optimize the common case of a SImode min/max against a constant
that is safe both for sign- and zero-extension.
E.g., consider the case
int f(unsigned int* a)
{
const int C = 1000;
return *a * 3 > C ? C : *a * 3;
}
where the constant C will yield the same result in DImode whether
sign- or zero-extended.
This should eventually go away once the lowering to RTL smartens up
and considers the precision/signedness and the value-ranges of the
operands to MIN_EXPR nad MAX_EXPR.
gcc/ChangeLog:
* config/riscv/bitmanip.md (*minmax): Additional pattern for
min/max against constants that are extension-invariant.
* config/riscv/iterators.md (minmax_optab): Add an iterator
that has only min and max rtl.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-min-max-02.c: New test.
Series-version: 2
Series-changes: 2
- fixes the use minmax_optab (was: bitmanip_optab), which didn't get
applied to the cherry-pick on the previous submission
Series-to: gcc-patches@gcc.gnu.org
Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
Series-cc: Vineet Gupta <vineetg@rivosinc.com>
Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
Series-cc: Kito Cheng <kito.cheng@gmail.com>
Series-cc: Jeff Law <jlaw@ventanamicro.com>
Diff:
---
gcc/config/riscv/bitmanip.md | 18 ++++++++++++++++++
gcc/config/riscv/iterators.md | 4 ++++
gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c | 14 ++++++++++++++
3 files changed, 36 insertions(+)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 2f89fd6aee1..db16f83b46e 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -368,6 +368,24 @@
"<bitmanip_insn>\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
+;; Optimize the common case of a SImode min/max against a constant
+;; that is safe both for sign- and zero-extension.
+(define_insn_and_split "*minmax"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extend:DI
+ (subreg:SI
+ (bitmanip_minmax:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
+ (match_operand:DI 2 "immediate_operand" "i"))
+ 0)))
+ (clobber (match_scratch:DI 3 "=&r"))
+ (clobber (match_scratch:DI 4 "=&r"))]
+ "TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
+ (set (match_dup 4) (match_dup 2))
+ (set (match_dup 0) (<minmax_optab>:DI (match_dup 3) (match_dup 4)))])
+
;; ZBS extension.
(define_insn "*bset<mode>"
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 50380ecfac9..cbbf61f6514 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -213,6 +213,10 @@
[(plus "add") (ior "or") (xor "xor") (and "and")])
; bitmanip code attributes
+(define_code_attr minmax_optab [(smin "smin")
+ (smax "smax")
+ (umin "umin")
+ (umax "umax")])
(define_code_attr bitmanip_optab [(smin "smin")
(smax "smax")
(umin "umin")
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c
new file mode 100644
index 00000000000..b462859f10f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba_zbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */
+
+int f(unsigned int* a)
+{
+ const int C = 1000;
+ return *a * 3 > C ? C : *a * 3;
+}
+
+/* { dg-final { scan-assembler-times "minu" 1 } } */
+/* { dg-final { scan-assembler-times "sext.w" 1 } } */
+/* { dg-final { scan-assembler-not "zext.w" } } */
+
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-11-18 20:22 UTC | newest]
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