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* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori
@ 2022-11-15 14:02 Philipp Tomsich
0 siblings, 0 replies; 2+ messages in thread
From: Philipp Tomsich @ 2022-11-15 14:02 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0533c214155dc1493eb5d972cd20b0c18d532edd
commit 0533c214155dc1493eb5d972cd20b0c18d532edd
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Thu May 12 15:11:20 2022 +0200
RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori
We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1"
by splitting it into a zero-extraction (bext) and an xori. This both
avoids burning a register on a temporary and generates a sequence that
clearly captures 'extract bit, then invert bit'.
This change improves the previously generated
srl a0,a0,a1
not a0,a0
andi a0,a0,1
into
bext a0,a0,a1
xori a0,a0,1
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
gcc/ChangeLog:
* config/riscv/bitmanip.md: Add split covering
"(a & (1 << BIT_NO)) ? 0 : 1".
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbs-bext.c: Add testcases.
* gcc.target/riscv/zbs-bexti.c: Add testcases.
Series-to: gcc-patches@gcc.gnu.org
Series-cc: Kito Cheng <kito.cheng@gmail.com>
Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
Series-cc: Vineet Gupta <vineetg@rivosinc.com>
Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
Series-cc: Jeff Law <jlaw@ventanamicro.com>
Diff:
---
gcc/config/riscv/bitmanip.md | 13 +++++++++++++
gcc/testsuite/gcc.target/riscv/zbs-bext.c | 10 ++++++++--
gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 10 ++++++++--
3 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index a5170baceaf..d639760e1e2 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -685,3 +685,16 @@
"TARGET_ZBS"
[(set (match_dup 0) (zero_extract:GPR (match_dup 1) (const_int 1) (match_dup 2)))
(set (match_dup 0) (plus:GPR (match_dup 0) (const_int -1)))])
+
+;; Split for "(a & (1 << BIT_NO)) ? 0 : 1":
+;; We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1",
+;; so we don't have to use a temporary. Instead we extract the bit and then
+;; invert bit 0 ("a ^ 1") only.
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (not:X (lshiftrt:X (match_operand:X 1 "register_operand")
+ (subreg:QI (match_operand:X 2 "register_operand") 0)))
+ (const_int 1)))]
+ "TARGET_ZBS"
+ [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
+ (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))])
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext.c b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
index 8de9c5a167c..a8aadb60390 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-bext.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
@@ -23,16 +23,22 @@ long bext64_1(long a, char bitno)
long bext64_2(long a, char bitno)
{
- return (a & (1UL << bitno)) ? 0 : -1;
+ return (a & (1UL << bitno)) ? 0 : 1;
}
long bext64_3(long a, char bitno)
+{
+ return (a & (1UL << bitno)) ? 0 : -1;
+}
+
+long bext64_4(long a, char bitno)
{
return (a & (1UL << bitno)) ? -1 : 0;
}
/* { dg-final { scan-assembler-times "bexti\t" 1 } } */
-/* { dg-final { scan-assembler-times "bext\t" 4 } } */
+/* { dg-final { scan-assembler-times "bext\t" 5 } } */
+/* { dg-final { scan-assembler-times "xori\t|snez\t" 1 } } */
/* { dg-final { scan-assembler-times "addi\t" 1 } } */
/* { dg-final { scan-assembler-times "neg\t" 1 } } */
/* { dg-final { scan-assembler-not "andi" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
index 30b69c9bc3e..c15098eb6cc 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
@@ -12,14 +12,20 @@ long bexti64_1(long a, char bitno)
long bexti64_2(long a, char bitno)
{
- return (a & (1UL << BIT_NO)) ? 0 : -1;
+ return (a & (1UL << BIT_NO)) ? 0 : 1;
}
long bexti64_3(long a, char bitno)
+{
+ return (a & (1UL << BIT_NO)) ? 0 : -1;
+}
+
+long bexti64_4(long a, char bitno)
{
return (a & (1UL << BIT_NO)) ? -1 : 0;
}
-/* { dg-final { scan-assembler-times "bexti\t" 3 } } */
+/* { dg-final { scan-assembler-times "bexti\t" 4 } } */
+/* { dg-final { scan-assembler-times "xori\t|snez\t" 1 } } */
/* { dg-final { scan-assembler-times "addi\t" 1 } } */
/* { dg-final { scan-assembler-times "neg\t" 1 } } */
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori
@ 2022-11-15 15:00 Philipp Tomsich
0 siblings, 0 replies; 2+ messages in thread
From: Philipp Tomsich @ 2022-11-15 15:00 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0a908783d1a16cb8a654e2426f4cd1b792db4e41
commit 0a908783d1a16cb8a654e2426f4cd1b792db4e41
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Thu May 12 15:11:20 2022 +0200
RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori
We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1"
by splitting it into a zero-extraction (bext) and an xori. This both
avoids burning a register on a temporary and generates a sequence that
clearly captures 'extract bit, then invert bit'.
This change improves the previously generated
srl a0,a0,a1
not a0,a0
andi a0,a0,1
into
bext a0,a0,a1
xori a0,a0,1
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
gcc/ChangeLog:
* config/riscv/bitmanip.md: Add split covering
"(a & (1 << BIT_NO)) ? 0 : 1".
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbs-bext.c: Add testcases.
* gcc.target/riscv/zbs-bexti.c: Add testcases.
Series-to: gcc-patches@gcc.gnu.org
Series-cc: Kito Cheng <kito.cheng@gmail.com>
Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
Series-cc: Vineet Gupta <vineetg@rivosinc.com>
Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
Series-cc: Jeff Law <jlaw@ventanamicro.com>
Diff:
---
gcc/config/riscv/bitmanip.md | 13 +++++++++++++
gcc/testsuite/gcc.target/riscv/zbs-bext.c | 10 ++++++++--
gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 10 ++++++++--
3 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index a5170baceafd..d639760e1e2d 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -685,3 +685,16 @@
"TARGET_ZBS"
[(set (match_dup 0) (zero_extract:GPR (match_dup 1) (const_int 1) (match_dup 2)))
(set (match_dup 0) (plus:GPR (match_dup 0) (const_int -1)))])
+
+;; Split for "(a & (1 << BIT_NO)) ? 0 : 1":
+;; We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1",
+;; so we don't have to use a temporary. Instead we extract the bit and then
+;; invert bit 0 ("a ^ 1") only.
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (not:X (lshiftrt:X (match_operand:X 1 "register_operand")
+ (subreg:QI (match_operand:X 2 "register_operand") 0)))
+ (const_int 1)))]
+ "TARGET_ZBS"
+ [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
+ (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))])
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext.c b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
index 8de9c5a167c6..a8aadb603909 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-bext.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
@@ -23,16 +23,22 @@ long bext64_1(long a, char bitno)
long bext64_2(long a, char bitno)
{
- return (a & (1UL << bitno)) ? 0 : -1;
+ return (a & (1UL << bitno)) ? 0 : 1;
}
long bext64_3(long a, char bitno)
+{
+ return (a & (1UL << bitno)) ? 0 : -1;
+}
+
+long bext64_4(long a, char bitno)
{
return (a & (1UL << bitno)) ? -1 : 0;
}
/* { dg-final { scan-assembler-times "bexti\t" 1 } } */
-/* { dg-final { scan-assembler-times "bext\t" 4 } } */
+/* { dg-final { scan-assembler-times "bext\t" 5 } } */
+/* { dg-final { scan-assembler-times "xori\t|snez\t" 1 } } */
/* { dg-final { scan-assembler-times "addi\t" 1 } } */
/* { dg-final { scan-assembler-times "neg\t" 1 } } */
/* { dg-final { scan-assembler-not "andi" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
index 30b69c9bc3e5..c15098eb6ccd 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
@@ -12,14 +12,20 @@ long bexti64_1(long a, char bitno)
long bexti64_2(long a, char bitno)
{
- return (a & (1UL << BIT_NO)) ? 0 : -1;
+ return (a & (1UL << BIT_NO)) ? 0 : 1;
}
long bexti64_3(long a, char bitno)
+{
+ return (a & (1UL << BIT_NO)) ? 0 : -1;
+}
+
+long bexti64_4(long a, char bitno)
{
return (a & (1UL << BIT_NO)) ? -1 : 0;
}
-/* { dg-final { scan-assembler-times "bexti\t" 3 } } */
+/* { dg-final { scan-assembler-times "bexti\t" 4 } } */
+/* { dg-final { scan-assembler-times "xori\t|snez\t" 1 } } */
/* { dg-final { scan-assembler-times "addi\t" 1 } } */
/* { dg-final { scan-assembler-times "neg\t" 1 } } */
^ permalink raw reply [flat|nested] 2+ messages in thread
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2022-11-15 14:02 [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori Philipp Tomsich
2022-11-15 15:00 Philipp Tomsich
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