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From: Philipp Tomsich <ptomsich@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Ventana-VT1 supports XVentanaCondOps
Date: Tue, 15 Nov 2022 15:00:22 +0000 (GMT)	[thread overview]
Message-ID: <20221115150022.DE3613898380@sourceware.org> (raw)

https://gcc.gnu.org/g:21cbb5b4e4ac10d4c43dd44016113286ce63098d

commit 21cbb5b4e4ac10d4c43dd44016113286ce63098d
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sun Nov 13 21:50:24 2022 +0100

    RISC-V: Ventana-VT1 supports XVentanaCondOps
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-cores.def (RISCV_CORE): Update the
            Ventana-VT1 definition to include the xventanacondops
            extension.
    
    Commit-changes: 2
    - New in v2.

Diff:
---
 gcc/config/riscv/riscv-cores.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index aef1e92ae24e..9e38e9dc72e6 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -74,6 +74,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
-RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei",	"ventana-vt1")
+RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops",	"ventana-vt1")
 
 #undef RISCV_CORE

             reply	other threads:[~2022-11-15 15:00 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-15 15:00 Philipp Tomsich [this message]
  -- strict thread matches above, loose matches on Subject: below --
2022-12-01 13:23 Philipp Tomsich
2022-11-18 20:26 Philipp Tomsich
2022-11-18 20:23 Philipp Tomsich
2022-11-18 11:35 Philipp Tomsich
2022-11-17 22:26 Philipp Tomsich
2022-11-15 14:02 Philipp Tomsich

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