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* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Ventana-VT1 supports XVentanaCondOps
@ 2022-11-15 15:00 Philipp Tomsich
  0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2022-11-15 15:00 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:21cbb5b4e4ac10d4c43dd44016113286ce63098d

commit 21cbb5b4e4ac10d4c43dd44016113286ce63098d
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sun Nov 13 21:50:24 2022 +0100

    RISC-V: Ventana-VT1 supports XVentanaCondOps
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-cores.def (RISCV_CORE): Update the
            Ventana-VT1 definition to include the xventanacondops
            extension.
    
    Commit-changes: 2
    - New in v2.

Diff:
---
 gcc/config/riscv/riscv-cores.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index aef1e92ae24e..9e38e9dc72e6 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -74,6 +74,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
-RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei",	"ventana-vt1")
+RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops",	"ventana-vt1")
 
 #undef RISCV_CORE

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Ventana-VT1 supports XVentanaCondOps
@ 2022-12-01 13:23 Philipp Tomsich
  0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2022-12-01 13:23 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:bfb9bc38ee9431851fa61197f9d3d281fbf58c4d

commit bfb9bc38ee9431851fa61197f9d3d281fbf58c4d
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sun Nov 13 21:50:24 2022 +0100

    RISC-V: Ventana-VT1 supports XVentanaCondOps
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-cores.def (RISCV_CORE): Update the
            Ventana-VT1 definition to include the xventanacondops
            extension.
    
    Commit-changes: 2
    - New in v2.

Diff:
---
 gcc/config/riscv/riscv-cores.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index aef1e92ae24..9e38e9dc72e 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -74,6 +74,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
-RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei",	"ventana-vt1")
+RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops",	"ventana-vt1")
 
 #undef RISCV_CORE

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Ventana-VT1 supports XVentanaCondOps
@ 2022-11-18 20:26 Philipp Tomsich
  0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2022-11-18 20:26 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:e4d96fa98721c92d6116480003c49800fd9db904

commit e4d96fa98721c92d6116480003c49800fd9db904
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sun Nov 13 21:50:24 2022 +0100

    RISC-V: Ventana-VT1 supports XVentanaCondOps
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-cores.def (RISCV_CORE): Update the
            Ventana-VT1 definition to include the xventanacondops
            extension.
    
    Commit-changes: 2
    - New in v2.

Diff:
---
 gcc/config/riscv/riscv-cores.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index aef1e92ae24..9e38e9dc72e 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -74,6 +74,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
-RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei",	"ventana-vt1")
+RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops",	"ventana-vt1")
 
 #undef RISCV_CORE

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Ventana-VT1 supports XVentanaCondOps
@ 2022-11-18 20:23 Philipp Tomsich
  0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2022-11-18 20:23 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:abfa0c7229e0416a2928e9fc9310b579ae38cd40

commit abfa0c7229e0416a2928e9fc9310b579ae38cd40
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sun Nov 13 21:50:24 2022 +0100

    RISC-V: Ventana-VT1 supports XVentanaCondOps
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-cores.def (RISCV_CORE): Update the
            Ventana-VT1 definition to include the xventanacondops
            extension.
    
    Commit-changes: 2
    - New in v2.

Diff:
---
 gcc/config/riscv/riscv-cores.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index aef1e92ae24..9e38e9dc72e 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -74,6 +74,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
-RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei",	"ventana-vt1")
+RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops",	"ventana-vt1")
 
 #undef RISCV_CORE

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Ventana-VT1 supports XVentanaCondOps
@ 2022-11-18 11:35 Philipp Tomsich
  0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2022-11-18 11:35 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:1b64c20f84194d395665e834e38c9f29bb81e654

commit 1b64c20f84194d395665e834e38c9f29bb81e654
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sun Nov 13 21:50:24 2022 +0100

    RISC-V: Ventana-VT1 supports XVentanaCondOps
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-cores.def (RISCV_CORE): Update the
            Ventana-VT1 definition to include the xventanacondops
            extension.
    
    Commit-changes: 2
    - New in v2.

Diff:
---
 gcc/config/riscv/riscv-cores.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index aef1e92ae24..9e38e9dc72e 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -74,6 +74,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
-RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei",	"ventana-vt1")
+RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops",	"ventana-vt1")
 
 #undef RISCV_CORE

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Ventana-VT1 supports XVentanaCondOps
@ 2022-11-17 22:26 Philipp Tomsich
  0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2022-11-17 22:26 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:84199cd547cc551644acf239e3bde3caf012f94c

commit 84199cd547cc551644acf239e3bde3caf012f94c
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sun Nov 13 21:50:24 2022 +0100

    RISC-V: Ventana-VT1 supports XVentanaCondOps
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-cores.def (RISCV_CORE): Update the
            Ventana-VT1 definition to include the xventanacondops
            extension.
    
    Commit-changes: 2
    - New in v2.

Diff:
---
 gcc/config/riscv/riscv-cores.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index aef1e92ae24..9e38e9dc72e 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -74,6 +74,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
-RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei",	"ventana-vt1")
+RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops",	"ventana-vt1")
 
 #undef RISCV_CORE

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Ventana-VT1 supports XVentanaCondOps
@ 2022-11-15 14:02 Philipp Tomsich
  0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2022-11-15 14:02 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:8960ad416991275e9a72e8bc4cad5884b452ae76

commit 8960ad416991275e9a72e8bc4cad5884b452ae76
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sun Nov 13 21:50:24 2022 +0100

    RISC-V: Ventana-VT1 supports XVentanaCondOps
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-cores.def (RISCV_CORE): Update the
            Ventana-VT1 definition to include the xventanacondops
            extension.
    
    Commit-changes: 2
    - New in v2.

Diff:
---
 gcc/config/riscv/riscv-cores.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index aef1e92ae24..9e38e9dc72e 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -74,6 +74,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
-RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei",	"ventana-vt1")
+RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops",	"ventana-vt1")
 
 #undef RISCV_CORE

^ permalink raw reply	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-12-01 13:23 UTC | newest]

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