[gcc/vrull/heads/for-upstream] (23 commits) riscv: Add support for strlen inline expansion

[gcc/vrull/heads/for-upstream] (23 commits) riscv: Add support for strlen inline expansion

[Philipp Tomsich]

The branch 'vrull/heads/for-upstream' was updated to point to:

 3e7bc4c007c... riscv: Add support for strlen inline expansion

It previously pointed to:

 1b1c78c3157... riscv: Add support for strlen inline expansion

Diff:

!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
-------------------------------------------------------------------

  1b1c78c... riscv: Add support for strlen inline expansion
  5ea97a2... riscv: Use by-pieces to do overlapping accesses in block_mo
  e5670d7... riscv: Move riscv_block_move_loop to separate file
  8f6a6b1... riscv: Enable overlap-by-pieces via tune param
  74922e2... riscv: bitmanip/zbb: Add prefix/postfix and enable visiblit
  f709428... RISC-V: Use .p2align for code-alignment
  457b5e7... ifcvt: add if-conversion to conditional-zero instructions
  abfa0c7... RISC-V: Ventana-VT1 supports XVentanaCondOps
  f2f4cda... RISC-V: Support immediates in XVentanaCondOps
  e0d5010... RISC-V: Add instruction fusion (for ventana-vt1)
  042df39... RISC-V: Add basic support for the Ventana-VT1 core
  337454d... RISC-V: Recognize bexti in negated if-conversion
  9bedb1c... RISC-V: Recognize sign-extract + and cases for XVentanaCond
  30f9ad1... RISC-V: Support noce_try_store_flag_mask as vt.maskc<n>
  2967ccf... RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if
  9ef7c58... RISC-V: Recognize xventanacondops extension
  e5c49c6... RISC-V: Replace zero_extendsidi2_shifted with generalized s
  e480cf9... ifcombine: fold two bit tests with different polarity
  f9ddc80... ifcombine: recognize single bit test of sign-bit
  015bb80... RISC-V: Implement movmisalign<mode> to enable SLP
  efd58b6... RISC-V: Optimise adding a (larger than simm12) constant to 
  8471d7e... RISC-V: No extensions for SImode min/max against safe const
  800ff37... RISC-V: branch-(not)equals-zero compares against $zero


Summary of changes (added commits):
-----------------------------------

  3e7bc4c... riscv: Add support for strlen inline expansion
  c58e424... riscv: Use by-pieces to do overlapping accesses in block_mo
  db2e8c8... riscv: Move riscv_block_move_loop to separate file
  72b806c... riscv: Enable overlap-by-pieces via tune param
  d7378ac... riscv: bitmanip/zbb: Add prefix/postfix and enable visiblit
  f4fca6a... RISC-V: Use .p2align for code-alignment
  09787e9... ifcvt: add if-conversion to conditional-zero instructions
  e4d96fa... RISC-V: Ventana-VT1 supports XVentanaCondOps
  71b468d... RISC-V: Support immediates in XVentanaCondOps
  7a87a85... RISC-V: Add instruction fusion (for ventana-vt1)
  9d95637... RISC-V: Add basic support for the Ventana-VT1 core
  95e8d5d... RISC-V: Recognize bexti in negated if-conversion
  95fbae4... RISC-V: Recognize sign-extract + and cases for XVentanaCond
  852dc40... RISC-V: Support noce_try_store_flag_mask as vt.maskc<n>
  01d2399... RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if
  d7568da... RISC-V: Recognize xventanacondops extension
  d669563... RISC-V: Replace zero_extendsidi2_shifted with generalized s
  d3e3ad7... ifcombine: fold two bit tests with different polarity
  d7d9ac7... ifcombine: recognize single bit test of sign-bit
  4139aa3... RISC-V: Implement movmisalign<mode> to enable SLP
  a9926c5... RISC-V: Optimise adding a (larger than simm12) constant to 
  3bace60... RISC-V: branch-(not)equals-zero compares against $zero
  3142265... RISC-V: No extensions for SImode min/max against safe const (*)

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