[gcc(refs/vendors/ARM/heads/morello)] simplify-rtx: Add missing capability constant handling

[gcc(refs/vendors/ARM/heads/morello)] simplify-rtx: Add missing capability constant handling

[Alex Coplan]

https://gcc.gnu.org/g:848b7db3d863416fdc787bc60631c5c80ede7ab4

commit 848b7db3d863416fdc787bc60631c5c80ede7ab4
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Sun Nov 20 11:22:13 2022 +0000

    simplify-rtx: Add missing capability constant handling
    
    A recent change to allow uses of INTCAP_TYPE C++ non-volatile const variable
    declarations in constexpr context revealed a latent problem in the form of an
    ICE in aarch64_asm_output_capability, triggered by the testcase
    g++.dg/cpp0x/pr88410.C.
    
    Here we ICE on the following rtx:
    
    (replace_address_value:CADI
      (const:CADI
        (pointer_plus:CADI
          (const_null:CADI) (const_int 36)))
      (plus:DI
        (subreg:DI
          (const:CADI
            (pointer_plus:CADI
              (const_null:CADI) (const_int 36))) 0)
        (const_int -32)))
    
    This shows that we are missing two RTL simplifications. Firstly, the subreg
    should be folded away: it should simplify to just (const_int 36).
    This would allow us to simplify the plus rtx to (const_int 4). The second
    missing simplification is that the replace_address_value should fold away to
    just:
    
    (replace_address_value:CADI (const_null:CADI) (const_int 4))
    
    which then gets canonicalized to:
    
    (const:CADI
      (pointer_plus:CADI
        (const_null:CADI) (const_int 4)))
    
    We note that simplify_subreg already handles taking the
    noncapability-mode lowpart subreg of CONST_NULL rtxes, but doesn't have
    any handling for taking such a subreg of non-zero capability constants.
    We add this handling to simplify_subreg.
    
    For the replace_address_value case, it looks like we already implement
    the appropriate simplification rule, namely:
    
    (replace_address_value:CM (X:M B CV1) CV2)
      --> (replace_address_value:CM B CV2)
    
    for any capability code X, provided CV1 is free of side effects. So this
    already works for e.g.:
    
    (replace_address_value:CADI
      (pointer_plus:CADI
        (const_null:CADI) (const_int 36))
      (const_int 4))
    
    but we don't currently handle the possibility of a CONST rtx wrapping
    the pointer_plus node, as generated by (e.g.) plus_constant. Thus, we
    teach simplify_binary_operation_1 to look through CONST rtxes in the
    implementation of the above rule.
    
    We further extend the simplify-rtx selftests to check we now correctly
    handle these cases.

Diff:
---
 gcc/simplify-rtx.c | 64 +++++++++++++++++++++++++++++++++++++++---------------
 1 file changed, 47 insertions(+), 17 deletions(-)

diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 0417149a42a..18f259e73b7 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -4450,13 +4450,18 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
 
       if (GET_CODE (op0) == CONST_NULL)
 	return simplify_gen_binary (POINTER_PLUS, mode, op0, op1);
-      else if (GET_CODE (op0) == REPLACE_ADDRESS_VALUE
-	    || GET_CODE (op0) == POINTER_PLUS
-	    || GET_CODE (op0) == ALIGN_ADDRESS_DOWN)
+
+      rtx x = op0;
+      if (GET_CODE (x) == CONST)
+	x = XEXP (x, 0);
+
+      if (GET_CODE (x) == REPLACE_ADDRESS_VALUE
+	    || GET_CODE (x) == POINTER_PLUS
+	    || GET_CODE (x) == ALIGN_ADDRESS_DOWN)
 	{
-	  if (!side_effects_p (XEXP (op0, 1)))
+	  if (!side_effects_p (XEXP (x, 1)))
 	    return simplify_gen_binary (REPLACE_ADDRESS_VALUE, mode,
-					XEXP (op0, 0), op1);
+					XEXP (x, 0), op1);
 	}
 
       if (GET_CODE (op1) == AND
@@ -7120,13 +7125,23 @@ simplify_subreg (machine_mode outermode, rtx op,
   if (GET_CODE (op) == CONST_VECTOR)
     byte = simplify_const_vector_byte_offset (op, byte);
 
-  if (CONST_NULL_P (op))
+  unsigned HOST_WIDE_INT cbyte;
+  if (byte.is_constant (&cbyte)
+      && known_eq (cbyte, subreg_lowpart_offset (outermode, innermode))
+      && noncapability_mode (innermode) == outermode)
     {
-      unsigned HOST_WIDE_INT cbyte;
-      if (byte.is_constant (&cbyte)
-	  && known_eq (cbyte, subreg_lowpart_offset (outermode, innermode))
-	  && noncapability_mode (innermode) == outermode)
+      if (CONST_NULL_P (op))
 	return gen_int_mode (0, outermode);
+
+      rtx x = op;
+      if (GET_CODE (x) == CONST)
+	x = XEXP (x, 0);
+
+      /* For a capability mode C and its non-capability mode NC:
+	 (subreg:NC (pointer_plus:C (const_null:C) (X:NC)))
+	 --> (X:NC).  */
+      if (POINTER_PLUS_P (x) && XEXP (x, 0) == CONST0_RTX (innermode))
+	return XEXP (x, 1);
     }
 
   if (multiple_p (byte, GET_MODE_UNIT_SIZE (innermode)))
@@ -8388,13 +8403,28 @@ test_align_address_down_simplifications ()
 }
 
 static void
-test_const_null_subreg ()
+test_cap_const_simplifications ()
 {
-  rtx inner = CONST0_RTX (CADImode);
-  rtx di_zero = CONST0_RTX (DImode);
-  ASSERT_EQ (simplify_subreg (DImode, inner, CADImode,
-			      subreg_lowpart_offset (DImode, CADImode)),
-	     di_zero);}
+  machine_mode cm = CADImode;
+  machine_mode om = DImode;
+
+  rtx const_null = CONST0_RTX (cm);
+  rtx di_zero = CONST0_RTX (om);
+  ASSERT_EQ (simplify_subreg (DImode, const_null, cm,
+			      subreg_lowpart_offset (om, cm)),
+	     di_zero);
+
+  rtx int42 = gen_int_mode (42, om);
+  rtx cap42 = plus_constant (cm, const_null, 42);
+  ASSERT_RTX_EQ (simplify_subreg (DImode, cap42, cm,
+				  subreg_lowpart_offset (om, cm)),
+		 int42);
+
+  rtx replaced = simplify_gen_binary (REPLACE_ADDRESS_VALUE, cm,
+				      plus_constant (cm, const_null, 4),
+				      int42);
+  ASSERT_RTX_EQ (replaced, cap42);
+}
 
 static void
 test_capability_simplifications ()
@@ -8403,7 +8433,7 @@ test_capability_simplifications ()
   test_pointer_plus_simplifications ();
   test_replace_address_value_simplifications ();
   test_align_address_down_simplifications ();
-  test_const_null_subreg ();
+  test_cap_const_simplifications ();
 }
 
 /* Run all of the selftests within this file.  */