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From: Alexandre Oliva <aoliva@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/aoliva/heads/testme)] [testsuite] [riscv] skip ssa-sink-18.c Date: Thu, 1 Dec 2022 07:39:53 +0000 (GMT) [thread overview] Message-ID: <20221201073953.2A5FD385B50C@sourceware.org> (raw) https://gcc.gnu.org/g:4028927b80f7cdc4edf438b39b2bf4028a9e5eff commit 4028927b80f7cdc4edf438b39b2bf4028a9e5eff Author: Alexandre Oliva <oliva@adacore.com> Date: Thu Dec 1 04:38:46 2022 -0300 [testsuite] [riscv] skip ssa-sink-18.c On riscv64, despite being lp64, we choose two IV candidates as on arm, which prevents some of the expected sinking. Add an xfail for it. for gcc/testsuite/ChangeLog * gcc.dg/tree-ssa/ssa-sink-18.c: xfail sink2 on riscv64. Change-Id: I2f4bacf3055a7dba52520280eac0ce52d19af5b2 TN: VB12-007 Diff: --- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c index 421c78eba50..9ac0fc6e4de 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c @@ -207,6 +207,9 @@ compute_on_bytes (uint8_t *in_data, int in_len, uint8_t *out_data, int out_len) from bb 31 to bb 33" When -m32, Power and X86 will sink 3 instructions, but arm ilp32 couldn't sink due to ivopts chooses two IV candidates instead of one, which is - expected, so this case is restricted to lp64 only so far. */ + expected, so this case is restricted to lp64 only so far. This different + ivopts choice affects riscv64 as well, probably because it also lacks + base+index addressing modes, so the ip[len] address computation can't be + made from the IV computation above. */ - /* { dg-final { scan-tree-dump-times "Sunk statements: 4" 1 "sink2" { target lp64 } } } */ + /* { dg-final { scan-tree-dump-times "Sunk statements: 4" 1 "sink2" { target lp64 xfail { riscv64-*-* } } } } */
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