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* [gcc(refs/users/meissner/heads/work103)] Update float 128-bit conversions, PR target/107299.
@ 2022-12-13 23:24 Michael Meissner
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From: Michael Meissner @ 2022-12-13 23:24 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1e144fbe7d85e66a71e2ecc6bd606a7852580698
commit 1e144fbe7d85e66a71e2ecc6bd606a7852580698
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Dec 13 18:22:43 2022 -0500
Update float 128-bit conversions, PR target/107299.
This patch fixes two tests that are still failing when long double is IEEE
128-bit after the previous 2 patches for PR target/107299 have been applied.
The tests are:
gcc.target/powerpc/convert-fp-128.c
gcc.target/powerpc/pr85657-3.c
This patch is a rewrite of the patch submitted on August 18th:
| https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599988.html
This patch reworks the conversions between 128-bit binary floating point types.
Previously, we would call rs6000_expand_float128_convert to do all conversions.
Now, we only define the conversions between the same representation that turn
into a NOP. The appropriate extend or truncate insn is generated, and after
register allocation, it is converted to a move.
This patch also fixes two places where we want to override the external name
for the conversion function, and the wrong optab was used. Previously,
rs6000_expand_float128_convert would handle the move or generate the call as
needed. Now, it lets the machine independent code generate the call. But if
we use the machine independent code to generate the call, we need to update the
name for two optabs where a truncate would be used in terms of converting
between the modes. This patch updates those two optabs.
I tested this patch on:
1) LE Power10 using --with-cpu=power10 --with-long-double-format=ieee
2) LE Power10 using --with-cpu=power10 --with-long-double-format=ibm
3) LE Power9 using --with-cpu=power9 --with-long-double-format=ibm
4) BE Power8 using --with-cpu=power8 --with-long-double-format=ibm
In the past I have also tested this exact patch on the following systems:
1) LE Power10 using --with-cpu=power9 --with-long-double-format=ibm
2) LE Power10 using --with-cpu=power8 --with-long-double-format=ibm
3) LE Power10 using --with-cpu=power10 --with-long-double-format=ibm
There were no regressions in the bootstrap process or running the tests (after
applying all 3 patches for PR target/107299). Can I check this patch into the
trunk?
2022-12-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/107299
* config/rs6000/rs6000.cc (init_float128_ieee): Use the correct
float_extend or float_truncate optab based on how the machine converts
between IEEE 128-bit and IBM 128-bit.
* config/rs6000/rs6000.md (IFKF): Delete.
(IFKF_reg): Delete.
(extendiftf2): Rewrite to be a move if IFmode and TFmode are both IBM
128-bit. Do not run if TFmode is IEEE 128-bit.
(extendifkf2): Delete.
(extendtfkf2): Delete.
(extendtfif2): Delete.
(trunciftf2): Delete.
(truncifkf2): Delete.
(trunckftf2): Delete.
(extendkftf2): Implement conversion of IEEE 128-bit types as a move.
(trunctfif2): Delete.
(trunctfkf2): Implement conversion of IEEE 128-bit types as a move.
(extend<mode>tf2_internal): Delete.
(extendtf<mode>2_internal): Delete.
Diff:
---
gcc/config/rs6000/rs6000.cc | 4 +-
gcc/config/rs6000/rs6000.md | 177 ++++++++++++--------------------------------
2 files changed, 50 insertions(+), 131 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 604f6a9ce33..0a20bfc8421 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -11134,11 +11134,11 @@ init_float128_ieee (machine_mode mode)
set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
- set_conv_libfunc (sext_optab, mode, IFmode, "__trunctfkf2");
+ set_conv_libfunc (trunc_optab, mode, IFmode, "__trunctfkf2");
if (mode != TFmode && FLOAT128_IBM_P (TFmode))
set_conv_libfunc (sext_optab, mode, TFmode, "__trunctfkf2");
- set_conv_libfunc (trunc_optab, IFmode, mode, "__extendkftf2");
+ set_conv_libfunc (sext_optab, IFmode, mode, "__extendkftf2");
if (mode != TFmode && FLOAT128_IBM_P (TFmode))
set_conv_libfunc (trunc_optab, TFmode, mode, "__extendkftf2");
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 6011f5bf76a..799af3c3ebe 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -543,12 +543,6 @@
; Iterator for 128-bit VSX types for pack/unpack
(define_mode_iterator FMOVE128_VSX [V1TI KF])
-; Iterators for converting to/from TFmode
-(define_mode_iterator IFKF [IF KF])
-
-; Constraints for moving IF/KFmode.
-(define_mode_attr IFKF_reg [(IF "d") (KF "wa")])
-
; Whether a floating point move is ok, don't allow SD without hardware FP
(define_mode_attr fmove_ok [(SF "")
(DF "")
@@ -9096,106 +9090,65 @@
"xxlor %x0,%x1,%x2"
[(set_attr "type" "veclogical")])
-;; Float128 conversion functions. These expand to library function calls.
-;; We use expand to convert from IBM double double to IEEE 128-bit
-;; and trunc for the opposite.
-(define_expand "extendiftf2"
- [(set (match_operand:TF 0 "gpc_reg_operand")
- (float_extend:TF (match_operand:IF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
-{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
-
-(define_expand "extendifkf2"
- [(set (match_operand:KF 0 "gpc_reg_operand")
- (float_extend:KF (match_operand:IF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
-{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
-
-(define_expand "extendtfkf2"
- [(set (match_operand:KF 0 "gpc_reg_operand")
- (float_extend:KF (match_operand:TF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
-{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
-
-(define_expand "extendtfif2"
- [(set (match_operand:IF 0 "gpc_reg_operand")
- (float_extend:IF (match_operand:TF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
-{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
-
-(define_expand "trunciftf2"
- [(set (match_operand:TF 0 "gpc_reg_operand")
- (float_truncate:TF (match_operand:IF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
-{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
-
-(define_expand "truncifkf2"
- [(set (match_operand:KF 0 "gpc_reg_operand")
- (float_truncate:KF (match_operand:IF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
-{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
-
-(define_expand "trunckftf2"
- [(set (match_operand:TF 0 "gpc_reg_operand")
- (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
+;; Float128 conversion functions. We only define the 'conversions' between two
+;; formats that use the same representation. We call the library function to
+;; convert between IEEE 128-bit and IBM 128-bit. We can't do these moves by
+;; using a SUBREG before register allocation. We set up the moves to prefer
+;; the output register being the same as the input register, which would enable
+;; the move to be deleted completely.
+(define_insn_and_split "extendkftf2"
+ [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa")
+ (float_extend:TF (match_operand:KF 1 "gpc_reg_operand" "0,wa")))]
+ "TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (TFmode)"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (match_dup 2))]
{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
+ operands[2] = gen_lowpart (TFmode, operands[1]);
+}
+ [(set_attr "type" "veclogical")])
-(define_expand "trunctfif2"
- [(set (match_operand:IF 0 "gpc_reg_operand")
- (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
+(define_insn_and_split "trunctfkf2"
+ [(set (match_operand:KF 0 "gpc_reg_operand" "=wa,wa")
+ (float_truncate:KF (match_operand:TF 1 "gpc_reg_operand" "0,wa")))]
+ "TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (TFmode)"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (match_dup 2))]
{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
+ operands[2] = gen_lowpart (KFmode, operands[1]);
+}
+ [(set_attr "type" "veclogical")])
-(define_insn_and_split "*extend<mode>tf2_internal"
- [(set (match_operand:TF 0 "gpc_reg_operand" "=<IFKF_reg>")
- (float_extend:TF
- (match_operand:IFKF 1 "gpc_reg_operand" "<IFKF_reg>")))]
- "TARGET_FLOAT128_TYPE
- && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (<MODE>mode)"
+(define_insn_and_split "extendtfif2"
+ [(set (match_operand:IF 0 "gpc_reg_operand" "=wa,wa,r,r")
+ (float_extend:IF (match_operand:TF 1 "gpc_reg_operand" "0,wa,0,r")))]
+ "TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)"
"#"
"&& reload_completed"
- [(set (match_dup 0) (match_dup 2))]
+ [(set (match_dup 0)
+ (match_dup 2))]
{
- operands[2] = gen_rtx_REG (TFmode, REGNO (operands[1]));
-})
+ operands[2] = gen_lowpart (IFmode, operands[1]);
+}
+ [(set_attr "num_insns" "2")
+ (set_attr "length" "8")])
-(define_insn_and_split "*extendtf<mode>2_internal"
- [(set (match_operand:IFKF 0 "gpc_reg_operand" "=<IFKF_reg>")
- (float_extend:IFKF
- (match_operand:TF 1 "gpc_reg_operand" "<IFKF_reg>")))]
- "TARGET_FLOAT128_TYPE
- && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (<MODE>mode)"
+(define_insn_and_split "extendiftf2"
+ [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa,r,r")
+ (float_extend:TF (match_operand:IF 1 "gpc_reg_operand" "0,wa,0,r")))]
+ "TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)"
"#"
"&& reload_completed"
- [(set (match_dup 0) (match_dup 2))]
+ [(set (match_dup 0)
+ (match_dup 2))]
{
- operands[2] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
-})
+ operands[2] = gen_lowpart (TFmode, operands[1]);
+}
+ [(set_attr "num_insns" "2")
+ (set_attr "length" "8")])
\f
;; Reload helper functions used by rs6000_secondary_reload. The patterns all
@@ -14919,40 +14872,6 @@
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
-;; Conversion between KFmode and TFmode if TFmode is ieee 128-bit floating
-;; point is a simple copy.
-(define_insn_and_split "extendkftf2"
- [(set (match_operand:TF 0 "vsx_register_operand" "=wa,?wa")
- (float_extend:TF (match_operand:KF 1 "vsx_register_operand" "0,wa")))]
- "TARGET_FLOAT128_TYPE && TARGET_IEEEQUAD"
- "@
- #
- xxlor %x0,%x1,%x1"
- "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
- [(const_int 0)]
-{
- emit_note (NOTE_INSN_DELETED);
- DONE;
-}
- [(set_attr "type" "*,veclogical")
- (set_attr "length" "0,4")])
-
-(define_insn_and_split "trunctfkf2"
- [(set (match_operand:KF 0 "vsx_register_operand" "=wa,?wa")
- (float_extend:KF (match_operand:TF 1 "vsx_register_operand" "0,wa")))]
- "TARGET_FLOAT128_TYPE && TARGET_IEEEQUAD"
- "@
- #
- xxlor %x0,%x1,%x1"
- "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
- [(const_int 0)]
-{
- emit_note (NOTE_INSN_DELETED);
- DONE;
-}
- [(set_attr "type" "*,veclogical")
- (set_attr "length" "0,4")])
-
(define_insn "trunc<mode>df2_hw"
[(set (match_operand:DF 0 "altivec_register_operand" "=v")
(float_truncate:DF
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2022-12-13 23:24 [gcc(refs/users/meissner/heads/work103)] Update float 128-bit conversions, PR target/107299 Michael Meissner
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