[gcc r13-4793] arm: correctly define __ARM_FEATURE_CLZ

[Richard Earnshaw <rearnsha@gcc.gnu.org>]

https://gcc.gnu.org/g:aa510619f8b650322c113d8593dd57afe6c6f9ae

commit r13-4793-gaa510619f8b650322c113d8593dd57afe6c6f9ae
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Mon Dec 19 15:01:49 2022 +0000

    arm: correctly define __ARM_FEATURE_CLZ
    
    The ACLE requires that __ARM_FEATURE_CLZ be defined if the hardware
    supports it; it's also clear that this doesn't mean the current ISA,
    so we must define this even when compiling for Thumb1 if the target
    supports CLZ in A32.
    
    This brings GCC into alignment with Clang.
    
    gcc/ChangeLog:
    
            * config/arm/arm-c.cc (__ARM_FEATURE_CLZ): Fix definition of
            preprocessor macro when target has CLZ in another ISA.

Diff:
---
 gcc/config/arm/arm-c.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc
index 86c56bf2680..202898fa041 100644
--- a/gcc/config/arm/arm-c.cc
+++ b/gcc/config/arm/arm-c.cc
@@ -238,8 +238,12 @@ arm_cpu_builtins (struct cpp_reader* pfile)
     builtin_define_with_int_value ("__ARM_FEATURE_LDREX",
 				   TARGET_ARM_FEATURE_LDREX);
 
+  /* ACLE says that __ARM_FEATURE_CLZ is defined if the hardware
+     supports it; it's also clear that this doesn't mean the current
+     ISA, so we define this even when compiling for Thumb1 if the
+     target supports CLZ in A32.  */
   def_or_undef_macro (pfile, "__ARM_FEATURE_CLZ",
-		      ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB)
+		      ((TARGET_ARM_ARCH >= 5 && arm_arch_notm)
 		       || TARGET_ARM_ARCH_ISA_THUMB >=2));
 
   def_or_undef_macro (pfile, "__ARM_FEATURE_NUMERIC_MAXMIN",