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From: Kito Cheng <kito@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-4866] RISC-V: Remove side effects of vsetvl pattern in RTL. Date: Fri, 23 Dec 2022 05:42:44 +0000 (GMT) [thread overview] Message-ID: <20221223054244.1E8B738582AB@sourceware.org> (raw) https://gcc.gnu.org/g:b47b33c799bd4874a4c81fb71708ff1c3dd150ff commit r13-4866-gb47b33c799bd4874a4c81fb71708ff1c3dd150ff Author: Ju-Zhe Zhong <juzhe.zhong@rivai.ai> Date: Tue Dec 20 22:56:49 2022 +0800 RISC-V: Remove side effects of vsetvl pattern in RTL. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Change it to no side effects. * config/riscv/vector.md (@vsetvl<mode>_no_side_effects): New pattern. Diff: --- gcc/config/riscv/riscv-vector-builtins-bases.cc | 2 +- gcc/config/riscv/vector.md | 26 +++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 75879dea25a..c1193dbbfb5 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -75,7 +75,7 @@ public: /* MU. */ e.add_input_operand (Pmode, gen_int_mode (0, Pmode)); - return e.generate_insn (code_for_vsetvl (Pmode)); + return e.generate_insn (code_for_vsetvl_no_side_effects (Pmode)); } }; diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 52ca6b3d25c..fd8e285a7e6 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -585,6 +585,32 @@ [(set_attr "type" "vsetvl") (set_attr "mode" "<MODE>")]) +;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects. +;; Since we have many optmization passes from "expand" to "reload_completed", +;; such pattern can allow us gain benefits of these optimizations. +(define_insn_and_split "@vsetvl<mode>_no_side_effects" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(match_operand:P 1 "csr_operand" "rK") + (match_operand 2 "const_int_operand" "i") + (match_operand 3 "const_int_operand" "i") + (match_operand 4 "const_int_operand" "i") + (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))] + "TARGET_VECTOR" + "#" + "&& epilogue_completed" + [(parallel + [(set (match_dup 0) + (unspec:P [(match_dup 1) (match_dup 2) (match_dup 3) + (match_dup 4) (match_dup 5)] UNSPEC_VSETVL)) + (set (reg:SI VL_REGNUM) + (unspec:SI [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_VSETVL)) + (set (reg:SI VTYPE_REGNUM) + (unspec:SI [(match_dup 2) (match_dup 3) (match_dup 4) + (match_dup 5)] UNSPEC_VSETVL))])] + "" + [(set_attr "type" "vsetvl") + (set_attr "mode" "SI")]) + ;; RVV machine description matching format ;; (define_insn "" ;; [(set (match_operand:MODE 0)
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