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* [gcc(refs/users/meissner/heads/work104)] Undo last patch
@ 2023-01-05 2:27 Michael Meissner
0 siblings, 0 replies; only message in thread
From: Michael Meissner @ 2023-01-05 2:27 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:cba4266a532a2173533e72e02594f37b162955d2
commit cba4266a532a2173533e72e02594f37b162955d2
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Jan 4 21:27:43 2023 -0500
Undo last patch
Diff:
---
gcc/config/rs6000/rs6000-modes.def | 35 +++++---
gcc/config/rs6000/rs6000-modes.h | 36 ++++++++
gcc/config/rs6000/rs6000.cc | 10 ++-
gcc/config/rs6000/rs6000.h | 5 ++
gcc/config/rs6000/rs6000.md | 177 ++++++++++---------------------------
gcc/config/rs6000/t-rs6000 | 1 +
gcc/genmodes.cc | 57 ++----------
gcc/machmode.def | 7 +-
gcc/machmode.h | 2 +-
9 files changed, 130 insertions(+), 200 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def
index 82828964f8e..8ef910869c5 100644
--- a/gcc/config/rs6000/rs6000-modes.def
+++ b/gcc/config/rs6000/rs6000-modes.def
@@ -18,24 +18,39 @@
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
-/* We use precision 126, 127, and 128 to differentiate between the 3 128-bit
- floating point modes in these declarations because genmodes.cc wants to sort
- by the precision. We reset the precision back to 128 after
- initialization in the compiler. */
+/* We order the 3 128-bit floating point types so that IFmode (IBM 128-bit
+ floating point) is the 128-bit floating point type with the highest
+ precision (128 bits). This so that machine independent parts of the
+ compiler do not try to widen IFmode to TFmode on ISA 3.0 (power9) that has
+ hardware support for IEEE 128-bit. We set TFmode (long double mode) in
+ between, and KFmode (explicit __float128) below it.
+
+ Previously, IFmode and KFmode were defined to be fractional modes and TFmode
+ was the standard mode. Since IFmode does not define the normal arithmetic
+ insns (other than neg/abs), on a ISA 3.0 system, the machine independent
+ parts of the compiler would see that TFmode has the necessary hardware
+ support, and widen the operation from IFmode to TFmode. However, IEEE
+ 128-bit is not strictly a super-set of IBM extended double and the
+ conversion to/from IEEE 128-bit was a function call.
+
+ We now make IFmode the highest fractional mode, which means its values are
+ not considered for widening. Since we don't define insns for IFmode, the
+ IEEE 128-bit modes would not widen to IFmode. */
+
+#ifndef RS6000_MODES_H
+#include "config/rs6000/rs6000-modes.h"
+#endif
/* IBM 128-bit floating point. */
-FRACTIONAL_FLOAT_MODE (IF, 126, 16, ibm_extended_format);
-ADJUST_PRECISION(IF, 128);
+FRACTIONAL_FLOAT_MODE (IF, FLOAT_PRECISION_IFmode, 16, ibm_extended_format);
/* Explicit IEEE 128-bit floating point. */
-FRACTIONAL_FLOAT_MODE (KF, 127, 16, ieee_quad_format);
-ADJUST_PRECISION(KF, 128);
+FRACTIONAL_FLOAT_MODE (KF, FLOAT_PRECISION_KFmode, 16, ieee_quad_format);
/* 128-bit floating point, either IBM 128-bit or IEEE 128-bit. This is
adjusted in rs6000_option_override_internal to be the appropriate floating
point type. */
-FRACTIONAL_FLOAT_MODE (TF, 128, 16, ieee_quad_format);
-ADJUST_PRECISION(TF, 128);
+FRACTIONAL_FLOAT_MODE (TF, FLOAT_PRECISION_TFmode, 16, ieee_quad_format);
/* Add any extra modes needed to represent the condition code.
diff --git a/gcc/config/rs6000/rs6000-modes.h b/gcc/config/rs6000/rs6000-modes.h
new file mode 100644
index 00000000000..64abf886db3
--- /dev/null
+++ b/gcc/config/rs6000/rs6000-modes.h
@@ -0,0 +1,36 @@
+/* Definitions 128-bit floating point precisions used by PowerPC.
+ Copyright (C) 2018-2022 Free Software Foundation, Inc.
+ Contributed by Michael Meissner (meissner@linux.ibm.com)
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+/* We order the 3 128-bit floating point types so that IFmode (IBM 128-bit
+ floating point) is the 128-bit floating point type with the highest
+ precision (128 bits). This so that machine independent parts of the
+ compiler do not try to widen IFmode to TFmode on ISA 3.0 (power9) that has
+ hardware support for IEEE 128-bit. We set TFmode (long double mode) in
+ between, and KFmode (explicit __float128) below it.
+
+ We won't encounter conversion from IEEE 128-bit to IBM 128-bit because we
+ don't have insns to support the IBM 128-bit aritmetic operations. */
+
+#ifndef RS6000_MODES_H
+#define RS6000_MODES_H 1
+#define FLOAT_PRECISION_IFmode 128
+#define FLOAT_PRECISION_TFmode 127
+#define FLOAT_PRECISION_KFmode 126
+#endif /* RS6000_MODES_H */
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index ab643ad8925..585faedc4e6 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4115,7 +4115,7 @@ rs6000_option_override_internal (bool global_init_p)
128 into the precision used for TFmode. */
int default_long_double_size = (RS6000_DEFAULT_LONG_DOUBLE_SIZE == 64
? 64
- : 128);
+ : FLOAT_PRECISION_TFmode);
/* Set long double size before the IEEE 128-bit tests. */
if (!OPTION_SET_P (rs6000_long_double_type_size))
@@ -4127,8 +4127,10 @@ rs6000_option_override_internal (bool global_init_p)
else
rs6000_long_double_type_size = default_long_double_size;
}
+ else if (rs6000_long_double_type_size == FLOAT_PRECISION_TFmode)
+ ; /* The option value can be seen when cl_target_option_restore is called. */
else if (rs6000_long_double_type_size == 128)
- rs6000_long_double_type_size = 128;
+ rs6000_long_double_type_size = FLOAT_PRECISION_TFmode;
/* Set -mabi=ieeelongdouble on some old targets. In the future, power server
systems will also set long double to be IEEE 128-bit. AIX and Darwin
@@ -11176,11 +11178,11 @@ init_float128_ieee (machine_mode mode)
set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
- set_conv_libfunc (sext_optab, mode, IFmode, "__trunctfkf2");
+ set_conv_libfunc (trunc_optab, mode, IFmode, "__trunctfkf2");
if (mode != TFmode && FLOAT128_IBM_P (TFmode))
set_conv_libfunc (sext_optab, mode, TFmode, "__trunctfkf2");
- set_conv_libfunc (trunc_optab, IFmode, mode, "__extendkftf2");
+ set_conv_libfunc (sext_optab, IFmode, mode, "__extendkftf2");
if (mode != TFmode && FLOAT128_IBM_P (TFmode))
set_conv_libfunc (trunc_optab, TFmode, mode, "__extendkftf2");
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 440ab55a067..b4df22b6030 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -30,6 +30,11 @@
#include "config/rs6000/rs6000-opts.h"
#endif
+/* 128-bit floating point precision values. */
+#ifndef RS6000_MODES_H
+#include "config/rs6000/rs6000-modes.h"
+#endif
+
/* Definitions for the object file format. These are set at
compile-time. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3cae64a264a..203d0ba6a7f 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -543,12 +543,6 @@
; Iterator for 128-bit VSX types for pack/unpack
(define_mode_iterator FMOVE128_VSX [V1TI KF])
-; Iterators for converting to/from TFmode
-(define_mode_iterator IFKF [IF KF])
-
-; Constraints for moving IF/KFmode.
-(define_mode_attr IFKF_reg [(IF "d") (KF "wa")])
-
; Whether a floating point move is ok, don't allow SD without hardware FP
(define_mode_attr fmove_ok [(SF "")
(DF "")
@@ -9161,106 +9155,65 @@
"xxlor %x0,%x1,%x2"
[(set_attr "type" "veclogical")])
-;; Float128 conversion functions. These expand to library function calls.
-;; We use expand to convert from IBM double double to IEEE 128-bit
-;; and trunc for the opposite.
-(define_expand "extendiftf2"
- [(set (match_operand:TF 0 "gpc_reg_operand")
- (float_extend:TF (match_operand:IF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
-{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
-
-(define_expand "extendifkf2"
- [(set (match_operand:KF 0 "gpc_reg_operand")
- (float_extend:KF (match_operand:IF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
-{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
-
-(define_expand "extendtfkf2"
- [(set (match_operand:KF 0 "gpc_reg_operand")
- (float_extend:KF (match_operand:TF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
-{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
-
-(define_expand "extendtfif2"
- [(set (match_operand:IF 0 "gpc_reg_operand")
- (float_extend:IF (match_operand:TF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
-{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
-
-(define_expand "trunciftf2"
- [(set (match_operand:TF 0 "gpc_reg_operand")
- (float_truncate:TF (match_operand:IF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
-{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
-
-(define_expand "truncifkf2"
- [(set (match_operand:KF 0 "gpc_reg_operand")
- (float_truncate:KF (match_operand:IF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
-{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
-
-(define_expand "trunckftf2"
- [(set (match_operand:TF 0 "gpc_reg_operand")
- (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
+;; Float128 conversion functions. We only define the 'conversions' between two
+;; formats that use the same representation. We call the library function to
+;; convert between IEEE 128-bit and IBM 128-bit. We can't do these moves by
+;; using a SUBREG before register allocation. We set up the moves to prefer
+;; the output register being the same as the input register, which would enable
+;; the move to be deleted completely.
+(define_insn_and_split "extendkftf2"
+ [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa")
+ (float_extend:TF (match_operand:KF 1 "gpc_reg_operand" "0,wa")))]
+ "TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (TFmode)"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (match_dup 2))]
{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
+ operands[2] = gen_lowpart (TFmode, operands[1]);
+}
+ [(set_attr "type" "veclogical")])
-(define_expand "trunctfif2"
- [(set (match_operand:IF 0 "gpc_reg_operand")
- (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
+(define_insn_and_split "trunctfkf2"
+ [(set (match_operand:KF 0 "gpc_reg_operand" "=wa,wa")
+ (float_truncate:KF (match_operand:TF 1 "gpc_reg_operand" "0,wa")))]
+ "TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (TFmode)"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (match_dup 2))]
{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
+ operands[2] = gen_lowpart (KFmode, operands[1]);
+}
+ [(set_attr "type" "veclogical")])
-(define_insn_and_split "*extend<mode>tf2_internal"
- [(set (match_operand:TF 0 "gpc_reg_operand" "=<IFKF_reg>")
- (float_extend:TF
- (match_operand:IFKF 1 "gpc_reg_operand" "<IFKF_reg>")))]
- "TARGET_FLOAT128_TYPE
- && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (<MODE>mode)"
+(define_insn_and_split "extendtfif2"
+ [(set (match_operand:IF 0 "gpc_reg_operand" "=wa,wa,r,r")
+ (float_extend:IF (match_operand:TF 1 "gpc_reg_operand" "0,wa,0,r")))]
+ "TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)"
"#"
"&& reload_completed"
- [(set (match_dup 0) (match_dup 2))]
+ [(set (match_dup 0)
+ (match_dup 2))]
{
- operands[2] = gen_rtx_REG (TFmode, REGNO (operands[1]));
-})
+ operands[2] = gen_lowpart (IFmode, operands[1]);
+}
+ [(set_attr "num_insns" "2")
+ (set_attr "length" "8")])
-(define_insn_and_split "*extendtf<mode>2_internal"
- [(set (match_operand:IFKF 0 "gpc_reg_operand" "=<IFKF_reg>")
- (float_extend:IFKF
- (match_operand:TF 1 "gpc_reg_operand" "<IFKF_reg>")))]
- "TARGET_FLOAT128_TYPE
- && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (<MODE>mode)"
+(define_insn_and_split "extendiftf2"
+ [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa,r,r")
+ (float_extend:TF (match_operand:IF 1 "gpc_reg_operand" "0,wa,0,r")))]
+ "TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)"
"#"
"&& reload_completed"
- [(set (match_dup 0) (match_dup 2))]
+ [(set (match_dup 0)
+ (match_dup 2))]
{
- operands[2] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
-})
+ operands[2] = gen_lowpart (TFmode, operands[1]);
+}
+ [(set_attr "num_insns" "2")
+ (set_attr "length" "8")])
\f
;; Reload helper functions used by rs6000_secondary_reload. The patterns all
@@ -14983,40 +14936,6 @@
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
-;; Conversion between KFmode and TFmode if TFmode is ieee 128-bit floating
-;; point is a simple copy.
-(define_insn_and_split "extendkftf2"
- [(set (match_operand:TF 0 "vsx_register_operand" "=wa,?wa")
- (float_extend:TF (match_operand:KF 1 "vsx_register_operand" "0,wa")))]
- "TARGET_FLOAT128_TYPE && TARGET_IEEEQUAD"
- "@
- #
- xxlor %x0,%x1,%x1"
- "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
- [(const_int 0)]
-{
- emit_note (NOTE_INSN_DELETED);
- DONE;
-}
- [(set_attr "type" "*,veclogical")
- (set_attr "length" "0,4")])
-
-(define_insn_and_split "trunctfkf2"
- [(set (match_operand:KF 0 "vsx_register_operand" "=wa,?wa")
- (float_extend:KF (match_operand:TF 1 "vsx_register_operand" "0,wa")))]
- "TARGET_FLOAT128_TYPE && TARGET_IEEEQUAD"
- "@
- #
- xxlor %x0,%x1,%x1"
- "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
- [(const_int 0)]
-{
- emit_note (NOTE_INSN_DELETED);
- DONE;
-}
- [(set_attr "type" "*,veclogical")
- (set_attr "length" "0,4")])
-
(define_insn "trunc<mode>df2_hw"
[(set (match_operand:DF 0 "altivec_register_operand" "=v")
(float_truncate:DF
diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000
index 72bf66dddf2..597cea423ec 100644
--- a/gcc/config/rs6000/t-rs6000
+++ b/gcc/config/rs6000/t-rs6000
@@ -19,6 +19,7 @@
# <http://www.gnu.org/licenses/>.
TM_H += $(srcdir)/config/rs6000/rs6000-cpus.def
+TM_H += $(srcdir)/config/rs6000/rs6000-modes.h
PASSES_EXTRA += $(srcdir)/config/rs6000/rs6000-passes.def
EXTRA_GTYPE_DEPS += rs6000-builtins.h
diff --git a/gcc/genmodes.cc b/gcc/genmodes.cc
index 67914ae5630..2d418f09aab 100644
--- a/gcc/genmodes.cc
+++ b/gcc/genmodes.cc
@@ -77,8 +77,6 @@ struct mode_data
adjustment */
bool need_bytesize_adj; /* true if this mode needs dynamic size
adjustment */
- bool need_precision_adj; /* true if this mode needs dynamic precision
- adjustment */
unsigned int int_n; /* If nonzero, then __int<INT_N> will be defined */
bool boolean;
};
@@ -91,7 +89,7 @@ static const struct mode_data blank_mode = {
0, "<unknown>", MAX_MODE_CLASS,
0, -1U, -1U, -1U, -1U,
0, 0, 0, 0, 0, 0,
- "<unknown>", 0, 0, 0, 0, false, false, false, 0,
+ "<unknown>", 0, 0, 0, 0, false, false, 0,
false
};
@@ -116,7 +114,6 @@ static struct mode_adjust *adj_alignment;
static struct mode_adjust *adj_format;
static struct mode_adjust *adj_ibit;
static struct mode_adjust *adj_fbit;
-static struct mode_adjust *adj_precision;
/* Mode class operations. */
static enum mode_class
@@ -825,7 +822,6 @@ make_vector_mode (enum mode_class bclass,
#define ADJUST_FLOAT_FORMAT(M, X) _ADD_ADJUST (format, M, X, FLOAT, FLOAT)
#define ADJUST_IBIT(M, X) _ADD_ADJUST (ibit, M, X, ACCUM, UACCUM)
#define ADJUST_FBIT(M, X) _ADD_ADJUST (fbit, M, X, FRACT, UACCUM)
-#define ADJUST_PRECISION(M, X) _ADD_ADJUST (precision, M, X, FLOAT, FLOAT)
static int bits_per_unit;
static int max_bitsize_mode_any_int;
@@ -1216,8 +1212,7 @@ extern __inline__ __attribute__((__always_inline__, __gnu_inline__))\n\
unsigned short\n\
mode_unit_precision_inline (machine_mode mode)\n\
{\n\
- extern CONST_MODE_PRECISION unsigned short \n\
- mode_unit_precision[NUM_MACHINE_MODES];\n\
+ extern const unsigned short mode_unit_precision[NUM_MACHINE_MODES];\n\
gcc_assert (mode >= 0 && mode < NUM_MACHINE_MODES);\n\
switch (mode)\n\
{");
@@ -1365,8 +1360,7 @@ enum machine_mode\n{");
/* I can't think of a better idea, can you? */
printf ("#define CONST_MODE_NUNITS%s\n", adj_nunits ? "" : " const");
- printf ("#define CONST_MODE_PRECISION%s\n",
- adj_precision || adj_nunits ? "" : " const");
+ printf ("#define CONST_MODE_PRECISION%s\n", adj_nunits ? "" : " const");
printf ("#define CONST_MODE_SIZE%s\n",
adj_bytesize || adj_nunits ? "" : " const");
printf ("#define CONST_MODE_UNIT_SIZE%s\n", adj_bytesize ? "" : " const");
@@ -1485,7 +1479,7 @@ emit_mode_precision (void)
struct mode_data *m;
print_maybe_const_decl ("%spoly_uint16_pod", "mode_precision",
- "NUM_MACHINE_MODES", adj_precision || adj_nunits);
+ "NUM_MACHINE_MODES", adj_nunits);
for_all_modes (c, m)
if (m->precision != (unsigned int)-1)
@@ -1705,8 +1699,7 @@ emit_mode_unit_precision (void)
int c;
struct mode_data *m;
- print_maybe_const_decl ("%sunsigned short", "mode_unit_precision",
- "NUM_MACHINE_MODES", adj_precision);
+ print_decl ("unsigned short", "mode_unit_precision", "NUM_MACHINE_MODES");
for_all_modes (c, m)
{
@@ -1970,46 +1963,6 @@ emit_mode_adjustments (void)
printf ("\n /* %s:%d */\n REAL_MODE_FORMAT (E_%smode) = %s;\n",
a->file, a->line, a->mode->name, a->adjustment);
-
- /* Precision adjustments propagate too. */
- for (a = adj_precision; a; a = a->next)
- {
- printf ("\n /* %s:%d */\n s = %s;\n",
- a->file, a->line, a->adjustment);
- printf (" mode_unit_precision[E_%smode] = s;\n", a->mode->name);
-
- for (m = a->mode->contained; m; m = m->next_cont)
- {
- switch (m->cl)
- {
- case MODE_COMPLEX_INT:
- case MODE_COMPLEX_FLOAT:
- printf (" mode_unit_precision[E_%smode] = s;\n", m->name);
- break;
-
- case MODE_VECTOR_BOOL:
- /* Changes to BImode should not affect vector booleans. */
- break;
-
- case MODE_VECTOR_INT:
- case MODE_VECTOR_FLOAT:
- case MODE_VECTOR_FRACT:
- case MODE_VECTOR_UFRACT:
- case MODE_VECTOR_ACCUM:
- case MODE_VECTOR_UACCUM:
- printf (" mode_unit_precision[E_%smode] = %d*s;\n",
- m->name, m->ncomponents);
- break;
-
- default:
- internal_error (
- "mode %s is neither vector nor complex but contains %s",
- m->name, a->mode->name);
- /* NOTREACHED */
- }
- }
- }
-
puts ("}");
}
diff --git a/gcc/machmode.def b/gcc/machmode.def
index 343dabc1b2e..62e2ba10d45 100644
--- a/gcc/machmode.def
+++ b/gcc/machmode.def
@@ -171,10 +171,9 @@ along with GCC; see the file COPYING3. If not see
ADJUST_FLOAT_FORMAT (MODE, EXPR);
ADJUST_IBIT (MODE, EXPR);
ADJUST_FBIT (MODE, EXPR);
- ADJUST_PRECISION (MODE, EXPR);
- Arrange for the byte size, alignment, floating point format, ibit, fbit
- or precision mode of MODE to be adjustable at run time. EXPR will be
- executed once after processing all command line options, and should
+ Arrange for the byte size, alignment, floating point format, ibit,
+ or fbit of MODE to be adjustable at run time. EXPR will be executed
+ once after processing all command line options, and should
evaluate to the desired byte size, alignment, format, ibit or fbit.
Unlike a FORMAT argument, if you are adjusting a float format
diff --git a/gcc/machmode.h b/gcc/machmode.h
index e4e0caf9abb..f1865c1ef42 100644
--- a/gcc/machmode.h
+++ b/gcc/machmode.h
@@ -27,7 +27,7 @@ extern CONST_MODE_PRECISION poly_uint16_pod mode_precision[NUM_MACHINE_MODES];
extern const unsigned char mode_inner[NUM_MACHINE_MODES];
extern CONST_MODE_NUNITS poly_uint16_pod mode_nunits[NUM_MACHINE_MODES];
extern CONST_MODE_UNIT_SIZE unsigned char mode_unit_size[NUM_MACHINE_MODES];
-extern CONST_MODE_PRECISION unsigned short mode_unit_precision[NUM_MACHINE_MODES];
+extern const unsigned short mode_unit_precision[NUM_MACHINE_MODES];
extern const unsigned char mode_next[NUM_MACHINE_MODES];
extern const unsigned char mode_wider[NUM_MACHINE_MODES];
extern const unsigned char mode_2xwider[NUM_MACHINE_MODES];
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2023-01-05 2:27 [gcc(refs/users/meissner/heads/work104)] Undo last patch Michael Meissner
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