[gcc(refs/users/meissner/heads/work107)] Update fp conversions #2

[gcc(refs/users/meissner/heads/work107)] Update fp conversions #2

[Michael Meissner]

https://gcc.gnu.org/g:6ea2485fa5573e7133ee20f3ef8e7075288b2de6

commit 6ea2485fa5573e7133ee20f3ef8e7075288b2de6
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Jan 24 23:40:35 2023 -0500

    Update fp conversions #2
    
    2022-01-24   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000.md (any_fp_cvt): New code iterator.
            (fp_cvt): New code attribute.
            (extendkftf2): Replace with <fp_cvt>kftf2.
            (trunctfkf2): Replace with <fp_cvt>tfkf2.
            (extendiftf2): Replace with <fp_cvt>iftf2.
            (trunctfif2): Replace with <fp_cvt>tfif2.
            (<fp_cvt>kftf2): Add both float_extend and float_truncate versions to
            convert between 128-bit floating point types with the same format..
            (<fp_cvt>tfkf2): Likewise.
            (<fp_cvt>iftf2): Likewise.
            (<fp_cvt>tfif2): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.md | 28 ++++++++++++++++------------
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d57826290d0..7decb7f7974 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -633,6 +633,7 @@
 (define_code_iterator any_extend	[sign_extend zero_extend])
 (define_code_iterator any_fix		[fix unsigned_fix])
 (define_code_iterator any_float		[float unsigned_float])
+(define_code_iterator any_fp_cvt	[float_extend float_truncate])
 
 (define_code_attr u  [(sign_extend	"")
 		      (zero_extend	"u")
@@ -658,6 +659,9 @@
 		       (float		"")
 		       (unsigned_float	"uns")])
 
+(define_code_attr fp_cvt [(float_extend		"extend")
+			  (float_truncate	"trunc")])
+
 ; Various instructions that come in SI and DI forms.
 ; A generic w/d attribute, for things like cmpw/cmpd.
 (define_mode_attr wd [(QI    "b")
@@ -9161,9 +9165,9 @@
 ;; using a SUBREG before register allocation.  We set up the moves to prefer
 ;; the output register being the same as the input register, which would enable
 ;; the move to be deleted completely.
-(define_insn_and_split "extendkftf2"
+(define_insn_and_split "<fp_cvt>kftf2"
   [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa")
-	(float_extend:TF (match_operand:KF 1 "gpc_reg_operand" "0,wa")))]
+	(any_fp_cvt:TF (match_operand:KF 1 "gpc_reg_operand" "0,wa")))]
   "TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (TFmode)"
   "#"
   "&& reload_completed"
@@ -9174,9 +9178,9 @@
 }
   [(set_attr "type" "veclogical")])
 
-(define_insn_and_split "trunctfkf2"
+(define_insn_and_split "<fp_cvt>tfkf2"
   [(set (match_operand:KF 0 "gpc_reg_operand" "=wa,wa")
-	(float_truncate:KF (match_operand:TF 1 "gpc_reg_operand" "0,wa")))]
+	(any_fp_cvt:KF (match_operand:TF 1 "gpc_reg_operand" "0,wa")))]
   "TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (TFmode)"
   "#"
   "&& reload_completed"
@@ -9187,30 +9191,30 @@
 }
   [(set_attr "type" "veclogical")])
 
-(define_insn_and_split "extendtfif2"
-  [(set (match_operand:IF 0 "gpc_reg_operand" "=wa,wa,r,r")
-	(float_extend:IF (match_operand:TF 1 "gpc_reg_operand" "0,wa,0,r")))]
+(define_insn_and_split "<fp_cvt>iftf2"
+  [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa,r,r")
+	(any_fp_cvt:TF (match_operand:IF 1 "gpc_reg_operand" "0,wa,0,r")))]
   "TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)"
   "#"
   "&& reload_completed"
   [(set (match_dup 0)
 	(match_dup 2))]
 {
-  operands[2] = gen_lowpart (IFmode, operands[1]);
+  operands[2] = gen_lowpart (TFmode, operands[1]);
 }
   [(set_attr "num_insns" "2")
    (set_attr "length" "8")])
 
-(define_insn_and_split "extendiftf2"
-  [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa,r,r")
-	(float_extend:TF (match_operand:IF 1 "gpc_reg_operand" "0,wa,0,r")))]
+(define_insn_and_split "<fp_cvt>tfif2"
+  [(set (match_operand:IF 0 "gpc_reg_operand" "=wa,wa,r,r")
+	(any_fp_cvt:IF (match_operand:TF 1 "gpc_reg_operand" "0,wa,0,r")))]
   "TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)"
   "#"
   "&& reload_completed"
   [(set (match_dup 0)
 	(match_dup 2))]
 {
-  operands[2] = gen_lowpart (TFmode, operands[1]);
+  operands[2] = gen_lowpart (IFmode, operands[1]);
 }
   [(set_attr "num_insns" "2")
    (set_attr "length" "8")])