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From: Philipp Tomsich <ptomsich@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc r13-5495] aarch64: Update Ampere-1A (-mcpu=ampere1a) to include SM4
Date: Mon, 30 Jan 2023 14:50:27 +0000 (GMT)	[thread overview]
Message-ID: <20230130145027.A6DD13858D1E@sourceware.org> (raw)

https://gcc.gnu.org/g:1472ba52f3f94a626b62a93a1dc44ca448555ef8

commit r13-5495-g1472ba52f3f94a626b62a93a1dc44ca448555ef8
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Wed Jan 25 20:15:14 2023 +0100

    aarch64: Update Ampere-1A (-mcpu=ampere1a) to include SM4
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64-cores.def (AARCH64_CORE): Update
            ampere1a to include SM4.

Diff:
---
 gcc/config/aarch64/aarch64-cores.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index 2a0f52e1dd9..85fdfd8bf74 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -70,7 +70,7 @@ AARCH64_CORE("thunderxt83",   thunderxt83,   thunderx,  V8A,  (CRC, CRYPTO), thu
 
 /* Ampere Computing ('\xC0') cores. */
 AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (F16, RNG, AES, SHA3), ampere1, 0xC0, 0xac3, -1)
-AARCH64_CORE("ampere1a", ampere1a, cortexa57, V8_6A, (F16, RNG, AES, SHA3, MEMTAG), ampere1a, 0xC0, 0xac4, -1)
+AARCH64_CORE("ampere1a", ampere1a, cortexa57, V8_6A, (F16, RNG, AES, SHA3, SM4, MEMTAG), ampere1a, 0xC0, 0xac4, -1)
 /* Do not swap around "emag" and "xgene1",
    this order is required to handle variant correctly. */
 AARCH64_CORE("emag",        emag,      xgene1,    V8A,  (CRC, CRYPTO), emag, 0x50, 0x000, 3)

                 reply	other threads:[~2023-01-30 14:50 UTC|newest]

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