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* [gcc r13-5904] RISC-V: Add vadc C++ API tests
@ 2023-02-12 6:57 Kito Cheng
0 siblings, 0 replies; only message in thread
From: Kito Cheng @ 2023-02-12 6:57 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:b7e4f61c3e703f38c5621d5114e776d245abdf73
commit r13-5904-gb7e4f61c3e703f38c5621d5114e776d245abdf73
Author: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Date: Wed Feb 8 10:47:25 2023 +0800
RISC-V: Add vadc C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vadc_vvm-1.C: New test.
* g++.target/riscv/rvv/base/vadc_vvm-2.C: New test.
* g++.target/riscv/rvv/base/vadc_vvm-3.C: New test.
* g++.target/riscv/rvv/base/vadc_vvm_tu-1.C: New test.
* g++.target/riscv/rvv/base/vadc_vvm_tu-2.C: New test.
* g++.target/riscv/rvv/base/vadc_vvm_tu-3.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C: New test.
Diff:
---
.../g++.target/riscv/rvv/base/vadc_vvm-1.C | 292 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vvm-2.C | 292 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vvm-3.C | 292 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vvm_tu-1.C | 292 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vvm_tu-2.C | 292 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vvm_tu-3.C | 292 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C | 289 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C | 289 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C | 289 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C | 292 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C | 292 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C | 292 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C | 289 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C | 289 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C | 289 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C | 292 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C | 292 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C | 292 +++++++++++++++++++++
18 files changed, 5238 insertions(+)
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-1.C
new file mode 100644
index 00000000000..049b57fbd78
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc(vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8mf4_t test___riscv_vadc(vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8mf2_t test___riscv_vadc(vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8m1_t test___riscv_vadc(vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8m2_t test___riscv_vadc(vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8m4_t test___riscv_vadc(vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8m8_t test___riscv_vadc(vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16mf4_t test___riscv_vadc(vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16mf2_t test___riscv_vadc(vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16m1_t test___riscv_vadc(vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16m2_t test___riscv_vadc(vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16m4_t test___riscv_vadc(vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16m8_t test___riscv_vadc(vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32mf2_t test___riscv_vadc(vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32m1_t test___riscv_vadc(vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32m2_t test___riscv_vadc(vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32m4_t test___riscv_vadc(vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32m8_t test___riscv_vadc(vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint64m1_t test___riscv_vadc(vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint64m2_t test___riscv_vadc(vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint64m4_t test___riscv_vadc(vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint64m8_t test___riscv_vadc(vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8m1_t test___riscv_vadc(vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8m2_t test___riscv_vadc(vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8m4_t test___riscv_vadc(vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8m8_t test___riscv_vadc(vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16m1_t test___riscv_vadc(vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16m2_t test___riscv_vadc(vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16m4_t test___riscv_vadc(vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16m8_t test___riscv_vadc(vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32m1_t test___riscv_vadc(vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32m2_t test___riscv_vadc(vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32m4_t test___riscv_vadc(vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32m8_t test___riscv_vadc(vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint64m1_t test___riscv_vadc(vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint64m2_t test___riscv_vadc(vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint64m4_t test___riscv_vadc(vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint64m8_t test___riscv_vadc(vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-2.C
new file mode 100644
index 00000000000..d1798cb181c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc(vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8mf4_t test___riscv_vadc(vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8mf2_t test___riscv_vadc(vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8m1_t test___riscv_vadc(vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8m2_t test___riscv_vadc(vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8m4_t test___riscv_vadc(vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8m8_t test___riscv_vadc(vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16mf4_t test___riscv_vadc(vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16mf2_t test___riscv_vadc(vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16m1_t test___riscv_vadc(vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16m2_t test___riscv_vadc(vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16m4_t test___riscv_vadc(vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16m8_t test___riscv_vadc(vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32mf2_t test___riscv_vadc(vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32m1_t test___riscv_vadc(vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32m2_t test___riscv_vadc(vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32m4_t test___riscv_vadc(vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32m8_t test___riscv_vadc(vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint64m1_t test___riscv_vadc(vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint64m2_t test___riscv_vadc(vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint64m4_t test___riscv_vadc(vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint64m8_t test___riscv_vadc(vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8m1_t test___riscv_vadc(vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8m2_t test___riscv_vadc(vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8m4_t test___riscv_vadc(vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8m8_t test___riscv_vadc(vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16m1_t test___riscv_vadc(vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16m2_t test___riscv_vadc(vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16m4_t test___riscv_vadc(vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16m8_t test___riscv_vadc(vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32m1_t test___riscv_vadc(vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32m2_t test___riscv_vadc(vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32m4_t test___riscv_vadc(vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32m8_t test___riscv_vadc(vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint64m1_t test___riscv_vadc(vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint64m2_t test___riscv_vadc(vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint64m4_t test___riscv_vadc(vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint64m8_t test___riscv_vadc(vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-3.C
new file mode 100644
index 00000000000..1367c6e1deb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc(vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8mf4_t test___riscv_vadc(vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8mf2_t test___riscv_vadc(vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8m1_t test___riscv_vadc(vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8m2_t test___riscv_vadc(vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8m4_t test___riscv_vadc(vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8m8_t test___riscv_vadc(vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16mf4_t test___riscv_vadc(vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16mf2_t test___riscv_vadc(vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16m1_t test___riscv_vadc(vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16m2_t test___riscv_vadc(vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16m4_t test___riscv_vadc(vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16m8_t test___riscv_vadc(vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32mf2_t test___riscv_vadc(vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32m1_t test___riscv_vadc(vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32m2_t test___riscv_vadc(vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32m4_t test___riscv_vadc(vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32m8_t test___riscv_vadc(vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint64m1_t test___riscv_vadc(vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint64m2_t test___riscv_vadc(vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint64m4_t test___riscv_vadc(vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint64m8_t test___riscv_vadc(vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8m1_t test___riscv_vadc(vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8m2_t test___riscv_vadc(vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8m4_t test___riscv_vadc(vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8m8_t test___riscv_vadc(vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16m1_t test___riscv_vadc(vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16m2_t test___riscv_vadc(vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16m4_t test___riscv_vadc(vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16m8_t test___riscv_vadc(vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32m1_t test___riscv_vadc(vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32m2_t test___riscv_vadc(vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32m4_t test___riscv_vadc(vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32m8_t test___riscv_vadc(vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint64m1_t test___riscv_vadc(vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint64m2_t test___riscv_vadc(vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint64m4_t test___riscv_vadc(vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint64m8_t test___riscv_vadc(vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-1.C
new file mode 100644
index 00000000000..a4fe7cc8816
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-2.C
new file mode 100644
index 00000000000..941bb79e9a0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-3.C
new file mode 100644
index 00000000000..501ccfe3f32
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C
new file mode 100644
index 00000000000..dda88d2322b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8mf4_t test___riscv_vadc(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8mf2_t test___riscv_vadc(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8m1_t test___riscv_vadc(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8m2_t test___riscv_vadc(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8m4_t test___riscv_vadc(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8m8_t test___riscv_vadc(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16mf4_t test___riscv_vadc(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16mf2_t test___riscv_vadc(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16m1_t test___riscv_vadc(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16m2_t test___riscv_vadc(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16m4_t test___riscv_vadc(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16m8_t test___riscv_vadc(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32mf2_t test___riscv_vadc(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32m1_t test___riscv_vadc(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32m2_t test___riscv_vadc(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32m4_t test___riscv_vadc(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32m8_t test___riscv_vadc(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint64m1_t test___riscv_vadc(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint64m2_t test___riscv_vadc(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint64m4_t test___riscv_vadc(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint64m8_t test___riscv_vadc(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8m1_t test___riscv_vadc(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8m2_t test___riscv_vadc(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8m4_t test___riscv_vadc(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8m8_t test___riscv_vadc(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16m1_t test___riscv_vadc(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16m2_t test___riscv_vadc(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16m4_t test___riscv_vadc(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16m8_t test___riscv_vadc(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32m1_t test___riscv_vadc(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32m2_t test___riscv_vadc(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32m4_t test___riscv_vadc(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32m8_t test___riscv_vadc(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint64m1_t test___riscv_vadc(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint64m2_t test___riscv_vadc(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint64m4_t test___riscv_vadc(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint64m8_t test___riscv_vadc(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C
new file mode 100644
index 00000000000..f15dbdd1f53
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8mf4_t test___riscv_vadc(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8mf2_t test___riscv_vadc(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8m1_t test___riscv_vadc(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8m2_t test___riscv_vadc(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8m4_t test___riscv_vadc(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8m8_t test___riscv_vadc(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16mf4_t test___riscv_vadc(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16mf2_t test___riscv_vadc(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16m1_t test___riscv_vadc(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16m2_t test___riscv_vadc(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16m4_t test___riscv_vadc(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16m8_t test___riscv_vadc(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32mf2_t test___riscv_vadc(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32m1_t test___riscv_vadc(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32m2_t test___riscv_vadc(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32m4_t test___riscv_vadc(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32m8_t test___riscv_vadc(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint64m1_t test___riscv_vadc(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint64m2_t test___riscv_vadc(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint64m4_t test___riscv_vadc(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint64m8_t test___riscv_vadc(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8m1_t test___riscv_vadc(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8m2_t test___riscv_vadc(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8m4_t test___riscv_vadc(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8m8_t test___riscv_vadc(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16m1_t test___riscv_vadc(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16m2_t test___riscv_vadc(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16m4_t test___riscv_vadc(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16m8_t test___riscv_vadc(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32m1_t test___riscv_vadc(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32m2_t test___riscv_vadc(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32m4_t test___riscv_vadc(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32m8_t test___riscv_vadc(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint64m1_t test___riscv_vadc(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint64m2_t test___riscv_vadc(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint64m4_t test___riscv_vadc(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint64m8_t test___riscv_vadc(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C
new file mode 100644
index 00000000000..6671f0cb19e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8mf4_t test___riscv_vadc(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8mf2_t test___riscv_vadc(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8m1_t test___riscv_vadc(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8m2_t test___riscv_vadc(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8m4_t test___riscv_vadc(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8m8_t test___riscv_vadc(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16mf4_t test___riscv_vadc(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16mf2_t test___riscv_vadc(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16m1_t test___riscv_vadc(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16m2_t test___riscv_vadc(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16m4_t test___riscv_vadc(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16m8_t test___riscv_vadc(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32mf2_t test___riscv_vadc(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32m1_t test___riscv_vadc(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32m2_t test___riscv_vadc(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32m4_t test___riscv_vadc(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32m8_t test___riscv_vadc(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint64m1_t test___riscv_vadc(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint64m2_t test___riscv_vadc(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint64m4_t test___riscv_vadc(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint64m8_t test___riscv_vadc(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8m1_t test___riscv_vadc(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8m2_t test___riscv_vadc(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8m4_t test___riscv_vadc(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8m8_t test___riscv_vadc(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16m1_t test___riscv_vadc(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16m2_t test___riscv_vadc(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16m4_t test___riscv_vadc(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16m8_t test___riscv_vadc(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32m1_t test___riscv_vadc(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32m2_t test___riscv_vadc(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32m4_t test___riscv_vadc(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32m8_t test___riscv_vadc(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint64m1_t test___riscv_vadc(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint64m2_t test___riscv_vadc(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint64m4_t test___riscv_vadc(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint64m8_t test___riscv_vadc(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C
new file mode 100644
index 00000000000..e44ab9428c3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8mf4_t test___riscv_vadc(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8mf2_t test___riscv_vadc(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8m1_t test___riscv_vadc(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8m2_t test___riscv_vadc(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8m4_t test___riscv_vadc(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint8m8_t test___riscv_vadc(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16mf4_t test___riscv_vadc(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16mf2_t test___riscv_vadc(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16m1_t test___riscv_vadc(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16m2_t test___riscv_vadc(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16m4_t test___riscv_vadc(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint16m8_t test___riscv_vadc(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32mf2_t test___riscv_vadc(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32m1_t test___riscv_vadc(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32m2_t test___riscv_vadc(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32m4_t test___riscv_vadc(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint32m8_t test___riscv_vadc(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint64m1_t test___riscv_vadc(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint64m2_t test___riscv_vadc(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint64m4_t test___riscv_vadc(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vint64m8_t test___riscv_vadc(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8m1_t test___riscv_vadc(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8m2_t test___riscv_vadc(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8m4_t test___riscv_vadc(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint8m8_t test___riscv_vadc(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16m1_t test___riscv_vadc(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16m2_t test___riscv_vadc(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16m4_t test___riscv_vadc(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint16m8_t test___riscv_vadc(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32m1_t test___riscv_vadc(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32m2_t test___riscv_vadc(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32m4_t test___riscv_vadc(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint32m8_t test___riscv_vadc(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint64m1_t test___riscv_vadc(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint64m2_t test___riscv_vadc(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint64m4_t test___riscv_vadc(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+vuint64m8_t test___riscv_vadc(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C
new file mode 100644
index 00000000000..304a70922ba
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8mf4_t test___riscv_vadc(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8mf2_t test___riscv_vadc(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8m1_t test___riscv_vadc(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8m2_t test___riscv_vadc(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8m4_t test___riscv_vadc(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint8m8_t test___riscv_vadc(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16mf4_t test___riscv_vadc(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16mf2_t test___riscv_vadc(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16m1_t test___riscv_vadc(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16m2_t test___riscv_vadc(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16m4_t test___riscv_vadc(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint16m8_t test___riscv_vadc(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32mf2_t test___riscv_vadc(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32m1_t test___riscv_vadc(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32m2_t test___riscv_vadc(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32m4_t test___riscv_vadc(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint32m8_t test___riscv_vadc(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint64m1_t test___riscv_vadc(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint64m2_t test___riscv_vadc(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint64m4_t test___riscv_vadc(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vint64m8_t test___riscv_vadc(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8m1_t test___riscv_vadc(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8m2_t test___riscv_vadc(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8m4_t test___riscv_vadc(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint8m8_t test___riscv_vadc(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16m1_t test___riscv_vadc(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16m2_t test___riscv_vadc(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16m4_t test___riscv_vadc(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint16m8_t test___riscv_vadc(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32m1_t test___riscv_vadc(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32m2_t test___riscv_vadc(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32m4_t test___riscv_vadc(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint32m8_t test___riscv_vadc(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint64m1_t test___riscv_vadc(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint64m2_t test___riscv_vadc(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint64m4_t test___riscv_vadc(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+vuint64m8_t test___riscv_vadc(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C
new file mode 100644
index 00000000000..60618b5e49b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8mf4_t test___riscv_vadc(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8mf2_t test___riscv_vadc(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8m1_t test___riscv_vadc(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8m2_t test___riscv_vadc(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8m4_t test___riscv_vadc(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint8m8_t test___riscv_vadc(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16mf4_t test___riscv_vadc(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16mf2_t test___riscv_vadc(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16m1_t test___riscv_vadc(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16m2_t test___riscv_vadc(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16m4_t test___riscv_vadc(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint16m8_t test___riscv_vadc(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32mf2_t test___riscv_vadc(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32m1_t test___riscv_vadc(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32m2_t test___riscv_vadc(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32m4_t test___riscv_vadc(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint32m8_t test___riscv_vadc(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint64m1_t test___riscv_vadc(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint64m2_t test___riscv_vadc(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint64m4_t test___riscv_vadc(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vint64m8_t test___riscv_vadc(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8m1_t test___riscv_vadc(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8m2_t test___riscv_vadc(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8m4_t test___riscv_vadc(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint8m8_t test___riscv_vadc(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16m1_t test___riscv_vadc(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16m2_t test___riscv_vadc(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16m4_t test___riscv_vadc(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint16m8_t test___riscv_vadc(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32m1_t test___riscv_vadc(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32m2_t test___riscv_vadc(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32m4_t test___riscv_vadc(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint32m8_t test___riscv_vadc(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint64m1_t test___riscv_vadc(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint64m2_t test___riscv_vadc(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint64m4_t test___riscv_vadc(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+vuint64m8_t test___riscv_vadc(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc(op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C
new file mode 100644
index 00000000000..f290720169a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C
new file mode 100644
index 00000000000..b04fc74e2a6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C
new file mode 100644
index 00000000000..ce0fc4d43c3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C
new file mode 100644
index 00000000000..59f5a81b9b0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C
new file mode 100644
index 00000000000..b44e2195599
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C
new file mode 100644
index 00000000000..ed58ccf439d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
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2023-02-12 6:57 [gcc r13-5904] RISC-V: Add vadc C++ API tests Kito Cheng
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