[gcc r13-5916] RISC-V: Add vmerge C API tests

[gcc r13-5916] RISC-V: Add vmerge C API tests

[Kito Cheng]

https://gcc.gnu.org/g:c0ea34be11c0da54c18b010ab51b97fc95657a4a

commit r13-5916-gc0ea34be11c0da54c18b010ab51b97fc95657a4a
Author: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Date:   Fri Feb 10 05:57:13 2023 +0800

    RISC-V: Add vmerge C API tests
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/base/vmerge-1.c: New test.
            * gcc.target/riscv/rvv/base/vmerge-2.c: New test.
            * gcc.target/riscv/rvv/base/vmerge-3.c: New test.
            * gcc.target/riscv/rvv/base/vmerge-4.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vvm-1.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vvm-2.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vvm-3.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vvm-4.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vvm-5.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vvm-6.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vvm_tu-1.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vvm_tu-2.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vvm_tu-3.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vvm_tu-4.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vvm_tu-5.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vvm_tu-6.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vxm_rv32-1.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vxm_rv32-2.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vxm_rv32-3.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vxm_rv64-1.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vxm_rv64-2.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vxm_rv64-3.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-1.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-2.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-3.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-1.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-2.c: New test.
            * gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-3.c: New test.

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-1.c |  27 ++
 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-2.c |  47 ++++
 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-3.c |  78 ++++++
 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-4.c |  79 ++++++
 .../gcc.target/riscv/rvv/base/vmerge_vvm-1.c       |  69 +++++
 .../gcc.target/riscv/rvv/base/vmerge_vvm-2.c       |  69 +++++
 .../gcc.target/riscv/rvv/base/vmerge_vvm-3.c       |  69 +++++
 .../gcc.target/riscv/rvv/base/vmerge_vvm-4.c       | 292 +++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmerge_vvm-5.c       | 292 +++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmerge_vvm-6.c       | 292 +++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-1.c    |  69 +++++
 .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-2.c    |  69 +++++
 .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-3.c    |  69 +++++
 .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-4.c    | 292 +++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-5.c    | 292 +++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-6.c    | 292 +++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmerge_vxm_rv32-1.c  | 289 ++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmerge_vxm_rv32-2.c  | 289 ++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmerge_vxm_rv32-3.c  | 289 ++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmerge_vxm_rv64-1.c  | 292 +++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmerge_vxm_rv64-2.c  | 292 +++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmerge_vxm_rv64-3.c  | 292 +++++++++++++++++++++
 .../riscv/rvv/base/vmerge_vxm_tu_rv32-1.c          | 289 ++++++++++++++++++++
 .../riscv/rvv/base/vmerge_vxm_tu_rv32-2.c          | 289 ++++++++++++++++++++
 .../riscv/rvv/base/vmerge_vxm_tu_rv32-3.c          | 289 ++++++++++++++++++++
 .../riscv/rvv/base/vmerge_vxm_tu_rv64-1.c          | 292 +++++++++++++++++++++
 .../riscv/rvv/base/vmerge_vxm_tu_rv64-2.c          | 292 +++++++++++++++++++++
 .../riscv/rvv/base/vmerge_vxm_tu_rv64-3.c          | 292 +++++++++++++++++++++
 28 files changed, 5883 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-1.c
new file mode 100644
index 00000000000..8248a0d4d60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+#include "riscv_vector.h"
+
+void f1 (void * in, void *out)
+{
+  vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vint32m1_t v3 = __riscv_vmerge_vvm_i32m1 (v2, v2, mask, 4);
+  vint32m1_t v4 = __riscv_vmerge_vvm_i32m1_tu (v3, v2, v2, mask, 4);
+  __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+void f2 (void * in, void *out)
+{
+  vbool32_t mask = *(vbool32_t*)in;
+  asm volatile ("":::"memory");
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+  vint32m1_t v3 = __riscv_vmerge_vvm_i32m1 (v2, v2, mask, 4);
+  vint32m1_t v4 = __riscv_vmerge_vvm_i32m1_tu (v3, v2, v2, mask, 4);
+  __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-not {vmv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-2.c
new file mode 100644
index 00000000000..460699d2652
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-2.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+#include "riscv_vector.h"
+
+void f1 (void * in, void *out, int32_t x)
+{
+  vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vint32m1_t v3 = __riscv_vmerge_vxm_i32m1 (v2, -16, mask, 4);
+  vint32m1_t v4 = __riscv_vmerge_vxm_i32m1_tu (v3, v2, -16, mask, 4);
+  __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+void f2 (void * in, void *out, int32_t x)
+{
+  vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vint32m1_t v3 = __riscv_vmerge_vxm_i32m1 (v2, 15, mask, 4);
+  vint32m1_t v4 = __riscv_vmerge_vxm_i32m1_tu (v3, v2, 15, mask, 4);
+  __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+void f3 (void * in, void *out, int32_t x)
+{
+  vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vint32m1_t v3 = __riscv_vmerge_vxm_i32m1 (v2, -17, mask, 4);
+  vint32m1_t v4 = __riscv_vmerge_vxm_i32m1_tu (v3, v2, -17, mask, 4);
+  __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+void f4 (void * in, void *out, int32_t x)
+{
+  vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vint32m1_t v3 = __riscv_vmerge_vxm_i32m1 (v2, 16, mask, 4);
+  vint32m1_t v4 = __riscv_vmerge_vxm_i32m1_tu (v3, v2, 16, mask, 4);
+  __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {vmerge\.vim\s+v[0-9]+,\s*v[0-9]+,\s*-16,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmerge\.vim\s+v[0-9]+,\s*v[0-9]+,\s*15,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmerge\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-3.c
new file mode 100644
index 00000000000..7aaf12d65d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-3.c
@@ -0,0 +1,78 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void f0 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vmerge_vxm_i64m1 (v2, -16, mask, 4);
+  vint64m1_t v4 = __riscv_vmerge_vxm_i64m1 (v3, -16, mask, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f1 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vmerge_vxm_i64m1 (v2, 15, mask, 4);
+  vint64m1_t v4 = __riscv_vmerge_vxm_i64m1 (v3, 15, mask, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f2 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vmerge_vxm_i64m1 (v2, -17, mask, 4);
+  vint64m1_t v4 = __riscv_vmerge_vxm_i64m1 (v3, -17, mask, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f3 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vmerge_vxm_i64m1 (v2, 16, mask, 4);
+  vint64m1_t v4 = __riscv_vmerge_vxm_i64m1 (v3, 16, mask, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f4 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vmerge_vxm_i64m1 (v2, 0xAAAAAAAA, mask, 4);
+  vint64m1_t v4 = __riscv_vmerge_vxm_i64m1 (v3, 0xAAAAAAAA, mask, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f5 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vmerge_vxm_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, mask, 4);
+  vint64m1_t v4 = __riscv_vmerge_vxm_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, mask, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f6 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vmerge_vxm_i64m1 (v2, x, mask, 4);
+  vint64m1_t v4 = __riscv_vmerge_vxm_i64m1 (v3, x, mask, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {vmerge\.vim\s+v[0-9]+,\s*v[0-9]+,\s*-16,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmerge\.vim\s+v[0-9]+,\s*v[0-9]+,\s*15,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmerge\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 10 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-4.c
new file mode 100644
index 00000000000..0db880a0084
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-4.c
@@ -0,0 +1,79 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+
+#include "riscv_vector.h"
+
+void f0 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vmerge_vxm_i64m1 (v2, -16, mask, 4);
+  vint64m1_t v4 = __riscv_vmerge_vxm_i64m1 (v3, -16, mask, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f1 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vmerge_vxm_i64m1 (v2, 15, mask, 4);
+  vint64m1_t v4 = __riscv_vmerge_vxm_i64m1 (v3, 15, mask, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f2 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vmerge_vxm_i64m1 (v2, -17, mask, 4);
+  vint64m1_t v4 = __riscv_vmerge_vxm_i64m1 (v3, -17, mask, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f3 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vmerge_vxm_i64m1 (v2, 16, mask, 4);
+  vint64m1_t v4 = __riscv_vmerge_vxm_i64m1 (v3, 16, mask, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f4 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vmerge_vxm_i64m1 (v2, 0xAAAAAAA, mask, 4);
+  vint64m1_t v4 = __riscv_vmerge_vxm_i64m1 (v3, 0xAAAAAAA, mask, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f5 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vmerge_vxm_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, mask, 4);
+  vint64m1_t v4 = __riscv_vmerge_vxm_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, mask, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f6 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vmerge_vxm_i64m1 (v2, x, mask, 4);
+  vint64m1_t v4 = __riscv_vmerge_vxm_i64m1 (v3, x, mask, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {vmerge\.vim\s+v[0-9]+,\s*v[0-9]+,\s*-16,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmerge\.vim\s+v[0-9]+,\s*v[0-9]+,\s*15,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmerge\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-1.c
new file mode 100644
index 00000000000..5186164680e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-1.c
@@ -0,0 +1,69 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vfloat32mf2_t test___riscv_vmerge_vvm_f32mf2(vfloat32mf2_t op1,vfloat32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32mf2(op1,op2,selector,vl);
+}
+
+
+vfloat32m1_t test___riscv_vmerge_vvm_f32m1(vfloat32m1_t op1,vfloat32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m1(op1,op2,selector,vl);
+}
+
+
+vfloat32m2_t test___riscv_vmerge_vvm_f32m2(vfloat32m2_t op1,vfloat32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m2(op1,op2,selector,vl);
+}
+
+
+vfloat32m4_t test___riscv_vmerge_vvm_f32m4(vfloat32m4_t op1,vfloat32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m4(op1,op2,selector,vl);
+}
+
+
+vfloat32m8_t test___riscv_vmerge_vvm_f32m8(vfloat32m8_t op1,vfloat32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m8(op1,op2,selector,vl);
+}
+
+
+vfloat64m1_t test___riscv_vmerge_vvm_f64m1(vfloat64m1_t op1,vfloat64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m1(op1,op2,selector,vl);
+}
+
+
+vfloat64m2_t test___riscv_vmerge_vvm_f64m2(vfloat64m2_t op1,vfloat64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m2(op1,op2,selector,vl);
+}
+
+
+vfloat64m4_t test___riscv_vmerge_vvm_f64m4(vfloat64m4_t op1,vfloat64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m4(op1,op2,selector,vl);
+}
+
+
+vfloat64m8_t test___riscv_vmerge_vvm_f64m8(vfloat64m8_t op1,vfloat64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m8(op1,op2,selector,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-2.c
new file mode 100644
index 00000000000..a080e26d5d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-2.c
@@ -0,0 +1,69 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vfloat32mf2_t test___riscv_vmerge_vvm_f32mf2(vfloat32mf2_t op1,vfloat32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32mf2(op1,op2,selector,31);
+}
+
+
+vfloat32m1_t test___riscv_vmerge_vvm_f32m1(vfloat32m1_t op1,vfloat32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m1(op1,op2,selector,31);
+}
+
+
+vfloat32m2_t test___riscv_vmerge_vvm_f32m2(vfloat32m2_t op1,vfloat32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m2(op1,op2,selector,31);
+}
+
+
+vfloat32m4_t test___riscv_vmerge_vvm_f32m4(vfloat32m4_t op1,vfloat32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m4(op1,op2,selector,31);
+}
+
+
+vfloat32m8_t test___riscv_vmerge_vvm_f32m8(vfloat32m8_t op1,vfloat32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m8(op1,op2,selector,31);
+}
+
+
+vfloat64m1_t test___riscv_vmerge_vvm_f64m1(vfloat64m1_t op1,vfloat64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m1(op1,op2,selector,31);
+}
+
+
+vfloat64m2_t test___riscv_vmerge_vvm_f64m2(vfloat64m2_t op1,vfloat64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m2(op1,op2,selector,31);
+}
+
+
+vfloat64m4_t test___riscv_vmerge_vvm_f64m4(vfloat64m4_t op1,vfloat64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m4(op1,op2,selector,31);
+}
+
+
+vfloat64m8_t test___riscv_vmerge_vvm_f64m8(vfloat64m8_t op1,vfloat64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m8(op1,op2,selector,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-3.c
new file mode 100644
index 00000000000..8a4b56f36bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-3.c
@@ -0,0 +1,69 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vfloat32mf2_t test___riscv_vmerge_vvm_f32mf2(vfloat32mf2_t op1,vfloat32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32mf2(op1,op2,selector,32);
+}
+
+
+vfloat32m1_t test___riscv_vmerge_vvm_f32m1(vfloat32m1_t op1,vfloat32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m1(op1,op2,selector,32);
+}
+
+
+vfloat32m2_t test___riscv_vmerge_vvm_f32m2(vfloat32m2_t op1,vfloat32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m2(op1,op2,selector,32);
+}
+
+
+vfloat32m4_t test___riscv_vmerge_vvm_f32m4(vfloat32m4_t op1,vfloat32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m4(op1,op2,selector,32);
+}
+
+
+vfloat32m8_t test___riscv_vmerge_vvm_f32m8(vfloat32m8_t op1,vfloat32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m8(op1,op2,selector,32);
+}
+
+
+vfloat64m1_t test___riscv_vmerge_vvm_f64m1(vfloat64m1_t op1,vfloat64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m1(op1,op2,selector,32);
+}
+
+
+vfloat64m2_t test___riscv_vmerge_vvm_f64m2(vfloat64m2_t op1,vfloat64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m2(op1,op2,selector,32);
+}
+
+
+vfloat64m4_t test___riscv_vmerge_vvm_f64m4(vfloat64m4_t op1,vfloat64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m4(op1,op2,selector,32);
+}
+
+
+vfloat64m8_t test___riscv_vmerge_vvm_f64m8(vfloat64m8_t op1,vfloat64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m8(op1,op2,selector,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-4.c
new file mode 100644
index 00000000000..de77b2c8757
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-4.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vvm_i8mf8(vint8mf8_t op1,vint8mf8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf8(op1,op2,selector,vl);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vvm_i8mf4(vint8mf4_t op1,vint8mf4_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf4(op1,op2,selector,vl);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vvm_i8mf2(vint8mf2_t op1,vint8mf2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf2(op1,op2,selector,vl);
+}
+
+
+vint8m1_t test___riscv_vmerge_vvm_i8m1(vint8m1_t op1,vint8m1_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m1(op1,op2,selector,vl);
+}
+
+
+vint8m2_t test___riscv_vmerge_vvm_i8m2(vint8m2_t op1,vint8m2_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m2(op1,op2,selector,vl);
+}
+
+
+vint8m4_t test___riscv_vmerge_vvm_i8m4(vint8m4_t op1,vint8m4_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m4(op1,op2,selector,vl);
+}
+
+
+vint8m8_t test___riscv_vmerge_vvm_i8m8(vint8m8_t op1,vint8m8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m8(op1,op2,selector,vl);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vvm_i16mf4(vint16mf4_t op1,vint16mf4_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16mf4(op1,op2,selector,vl);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vvm_i16mf2(vint16mf2_t op1,vint16mf2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16mf2(op1,op2,selector,vl);
+}
+
+
+vint16m1_t test___riscv_vmerge_vvm_i16m1(vint16m1_t op1,vint16m1_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m1(op1,op2,selector,vl);
+}
+
+
+vint16m2_t test___riscv_vmerge_vvm_i16m2(vint16m2_t op1,vint16m2_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m2(op1,op2,selector,vl);
+}
+
+
+vint16m4_t test___riscv_vmerge_vvm_i16m4(vint16m4_t op1,vint16m4_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m4(op1,op2,selector,vl);
+}
+
+
+vint16m8_t test___riscv_vmerge_vvm_i16m8(vint16m8_t op1,vint16m8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m8(op1,op2,selector,vl);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vvm_i32mf2(vint32mf2_t op1,vint32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32mf2(op1,op2,selector,vl);
+}
+
+
+vint32m1_t test___riscv_vmerge_vvm_i32m1(vint32m1_t op1,vint32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m1(op1,op2,selector,vl);
+}
+
+
+vint32m2_t test___riscv_vmerge_vvm_i32m2(vint32m2_t op1,vint32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m2(op1,op2,selector,vl);
+}
+
+
+vint32m4_t test___riscv_vmerge_vvm_i32m4(vint32m4_t op1,vint32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m4(op1,op2,selector,vl);
+}
+
+
+vint32m8_t test___riscv_vmerge_vvm_i32m8(vint32m8_t op1,vint32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m8(op1,op2,selector,vl);
+}
+
+
+vint64m1_t test___riscv_vmerge_vvm_i64m1(vint64m1_t op1,vint64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m1(op1,op2,selector,vl);
+}
+
+
+vint64m2_t test___riscv_vmerge_vvm_i64m2(vint64m2_t op1,vint64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m2(op1,op2,selector,vl);
+}
+
+
+vint64m4_t test___riscv_vmerge_vvm_i64m4(vint64m4_t op1,vint64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m4(op1,op2,selector,vl);
+}
+
+
+vint64m8_t test___riscv_vmerge_vvm_i64m8(vint64m8_t op1,vint64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m8(op1,op2,selector,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vvm_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf8(op1,op2,selector,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vvm_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf4(op1,op2,selector,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vvm_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf2(op1,op2,selector,vl);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vvm_u8m1(vuint8m1_t op1,vuint8m1_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m1(op1,op2,selector,vl);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vvm_u8m2(vuint8m2_t op1,vuint8m2_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m2(op1,op2,selector,vl);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vvm_u8m4(vuint8m4_t op1,vuint8m4_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m4(op1,op2,selector,vl);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vvm_u8m8(vuint8m8_t op1,vuint8m8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m8(op1,op2,selector,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vvm_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16mf4(op1,op2,selector,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vvm_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16mf2(op1,op2,selector,vl);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vvm_u16m1(vuint16m1_t op1,vuint16m1_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m1(op1,op2,selector,vl);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vvm_u16m2(vuint16m2_t op1,vuint16m2_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m2(op1,op2,selector,vl);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vvm_u16m4(vuint16m4_t op1,vuint16m4_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m4(op1,op2,selector,vl);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vvm_u16m8(vuint16m8_t op1,vuint16m8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m8(op1,op2,selector,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vvm_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32mf2(op1,op2,selector,vl);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vvm_u32m1(vuint32m1_t op1,vuint32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m1(op1,op2,selector,vl);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vvm_u32m2(vuint32m2_t op1,vuint32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m2(op1,op2,selector,vl);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vvm_u32m4(vuint32m4_t op1,vuint32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m4(op1,op2,selector,vl);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vvm_u32m8(vuint32m8_t op1,vuint32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m8(op1,op2,selector,vl);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vvm_u64m1(vuint64m1_t op1,vuint64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m1(op1,op2,selector,vl);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vvm_u64m2(vuint64m2_t op1,vuint64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m2(op1,op2,selector,vl);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vvm_u64m4(vuint64m4_t op1,vuint64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m4(op1,op2,selector,vl);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vvm_u64m8(vuint64m8_t op1,vuint64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m8(op1,op2,selector,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-5.c
new file mode 100644
index 00000000000..3c11c7f0f98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-5.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vvm_i8mf8(vint8mf8_t op1,vint8mf8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf8(op1,op2,selector,31);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vvm_i8mf4(vint8mf4_t op1,vint8mf4_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf4(op1,op2,selector,31);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vvm_i8mf2(vint8mf2_t op1,vint8mf2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf2(op1,op2,selector,31);
+}
+
+
+vint8m1_t test___riscv_vmerge_vvm_i8m1(vint8m1_t op1,vint8m1_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m1(op1,op2,selector,31);
+}
+
+
+vint8m2_t test___riscv_vmerge_vvm_i8m2(vint8m2_t op1,vint8m2_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m2(op1,op2,selector,31);
+}
+
+
+vint8m4_t test___riscv_vmerge_vvm_i8m4(vint8m4_t op1,vint8m4_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m4(op1,op2,selector,31);
+}
+
+
+vint8m8_t test___riscv_vmerge_vvm_i8m8(vint8m8_t op1,vint8m8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m8(op1,op2,selector,31);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vvm_i16mf4(vint16mf4_t op1,vint16mf4_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16mf4(op1,op2,selector,31);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vvm_i16mf2(vint16mf2_t op1,vint16mf2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16mf2(op1,op2,selector,31);
+}
+
+
+vint16m1_t test___riscv_vmerge_vvm_i16m1(vint16m1_t op1,vint16m1_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m1(op1,op2,selector,31);
+}
+
+
+vint16m2_t test___riscv_vmerge_vvm_i16m2(vint16m2_t op1,vint16m2_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m2(op1,op2,selector,31);
+}
+
+
+vint16m4_t test___riscv_vmerge_vvm_i16m4(vint16m4_t op1,vint16m4_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m4(op1,op2,selector,31);
+}
+
+
+vint16m8_t test___riscv_vmerge_vvm_i16m8(vint16m8_t op1,vint16m8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m8(op1,op2,selector,31);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vvm_i32mf2(vint32mf2_t op1,vint32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32mf2(op1,op2,selector,31);
+}
+
+
+vint32m1_t test___riscv_vmerge_vvm_i32m1(vint32m1_t op1,vint32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m1(op1,op2,selector,31);
+}
+
+
+vint32m2_t test___riscv_vmerge_vvm_i32m2(vint32m2_t op1,vint32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m2(op1,op2,selector,31);
+}
+
+
+vint32m4_t test___riscv_vmerge_vvm_i32m4(vint32m4_t op1,vint32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m4(op1,op2,selector,31);
+}
+
+
+vint32m8_t test___riscv_vmerge_vvm_i32m8(vint32m8_t op1,vint32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m8(op1,op2,selector,31);
+}
+
+
+vint64m1_t test___riscv_vmerge_vvm_i64m1(vint64m1_t op1,vint64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m1(op1,op2,selector,31);
+}
+
+
+vint64m2_t test___riscv_vmerge_vvm_i64m2(vint64m2_t op1,vint64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m2(op1,op2,selector,31);
+}
+
+
+vint64m4_t test___riscv_vmerge_vvm_i64m4(vint64m4_t op1,vint64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m4(op1,op2,selector,31);
+}
+
+
+vint64m8_t test___riscv_vmerge_vvm_i64m8(vint64m8_t op1,vint64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m8(op1,op2,selector,31);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vvm_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf8(op1,op2,selector,31);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vvm_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf4(op1,op2,selector,31);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vvm_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf2(op1,op2,selector,31);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vvm_u8m1(vuint8m1_t op1,vuint8m1_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m1(op1,op2,selector,31);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vvm_u8m2(vuint8m2_t op1,vuint8m2_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m2(op1,op2,selector,31);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vvm_u8m4(vuint8m4_t op1,vuint8m4_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m4(op1,op2,selector,31);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vvm_u8m8(vuint8m8_t op1,vuint8m8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m8(op1,op2,selector,31);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vvm_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16mf4(op1,op2,selector,31);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vvm_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16mf2(op1,op2,selector,31);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vvm_u16m1(vuint16m1_t op1,vuint16m1_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m1(op1,op2,selector,31);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vvm_u16m2(vuint16m2_t op1,vuint16m2_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m2(op1,op2,selector,31);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vvm_u16m4(vuint16m4_t op1,vuint16m4_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m4(op1,op2,selector,31);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vvm_u16m8(vuint16m8_t op1,vuint16m8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m8(op1,op2,selector,31);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vvm_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32mf2(op1,op2,selector,31);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vvm_u32m1(vuint32m1_t op1,vuint32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m1(op1,op2,selector,31);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vvm_u32m2(vuint32m2_t op1,vuint32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m2(op1,op2,selector,31);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vvm_u32m4(vuint32m4_t op1,vuint32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m4(op1,op2,selector,31);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vvm_u32m8(vuint32m8_t op1,vuint32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m8(op1,op2,selector,31);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vvm_u64m1(vuint64m1_t op1,vuint64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m1(op1,op2,selector,31);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vvm_u64m2(vuint64m2_t op1,vuint64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m2(op1,op2,selector,31);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vvm_u64m4(vuint64m4_t op1,vuint64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m4(op1,op2,selector,31);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vvm_u64m8(vuint64m8_t op1,vuint64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m8(op1,op2,selector,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-6.c
new file mode 100644
index 00000000000..9ac153d5fac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-6.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vvm_i8mf8(vint8mf8_t op1,vint8mf8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf8(op1,op2,selector,32);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vvm_i8mf4(vint8mf4_t op1,vint8mf4_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf4(op1,op2,selector,32);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vvm_i8mf2(vint8mf2_t op1,vint8mf2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf2(op1,op2,selector,32);
+}
+
+
+vint8m1_t test___riscv_vmerge_vvm_i8m1(vint8m1_t op1,vint8m1_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m1(op1,op2,selector,32);
+}
+
+
+vint8m2_t test___riscv_vmerge_vvm_i8m2(vint8m2_t op1,vint8m2_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m2(op1,op2,selector,32);
+}
+
+
+vint8m4_t test___riscv_vmerge_vvm_i8m4(vint8m4_t op1,vint8m4_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m4(op1,op2,selector,32);
+}
+
+
+vint8m8_t test___riscv_vmerge_vvm_i8m8(vint8m8_t op1,vint8m8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m8(op1,op2,selector,32);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vvm_i16mf4(vint16mf4_t op1,vint16mf4_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16mf4(op1,op2,selector,32);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vvm_i16mf2(vint16mf2_t op1,vint16mf2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16mf2(op1,op2,selector,32);
+}
+
+
+vint16m1_t test___riscv_vmerge_vvm_i16m1(vint16m1_t op1,vint16m1_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m1(op1,op2,selector,32);
+}
+
+
+vint16m2_t test___riscv_vmerge_vvm_i16m2(vint16m2_t op1,vint16m2_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m2(op1,op2,selector,32);
+}
+
+
+vint16m4_t test___riscv_vmerge_vvm_i16m4(vint16m4_t op1,vint16m4_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m4(op1,op2,selector,32);
+}
+
+
+vint16m8_t test___riscv_vmerge_vvm_i16m8(vint16m8_t op1,vint16m8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m8(op1,op2,selector,32);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vvm_i32mf2(vint32mf2_t op1,vint32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32mf2(op1,op2,selector,32);
+}
+
+
+vint32m1_t test___riscv_vmerge_vvm_i32m1(vint32m1_t op1,vint32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m1(op1,op2,selector,32);
+}
+
+
+vint32m2_t test___riscv_vmerge_vvm_i32m2(vint32m2_t op1,vint32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m2(op1,op2,selector,32);
+}
+
+
+vint32m4_t test___riscv_vmerge_vvm_i32m4(vint32m4_t op1,vint32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m4(op1,op2,selector,32);
+}
+
+
+vint32m8_t test___riscv_vmerge_vvm_i32m8(vint32m8_t op1,vint32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m8(op1,op2,selector,32);
+}
+
+
+vint64m1_t test___riscv_vmerge_vvm_i64m1(vint64m1_t op1,vint64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m1(op1,op2,selector,32);
+}
+
+
+vint64m2_t test___riscv_vmerge_vvm_i64m2(vint64m2_t op1,vint64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m2(op1,op2,selector,32);
+}
+
+
+vint64m4_t test___riscv_vmerge_vvm_i64m4(vint64m4_t op1,vint64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m4(op1,op2,selector,32);
+}
+
+
+vint64m8_t test___riscv_vmerge_vvm_i64m8(vint64m8_t op1,vint64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m8(op1,op2,selector,32);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vvm_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf8(op1,op2,selector,32);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vvm_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf4(op1,op2,selector,32);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vvm_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf2(op1,op2,selector,32);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vvm_u8m1(vuint8m1_t op1,vuint8m1_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m1(op1,op2,selector,32);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vvm_u8m2(vuint8m2_t op1,vuint8m2_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m2(op1,op2,selector,32);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vvm_u8m4(vuint8m4_t op1,vuint8m4_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m4(op1,op2,selector,32);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vvm_u8m8(vuint8m8_t op1,vuint8m8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m8(op1,op2,selector,32);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vvm_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16mf4(op1,op2,selector,32);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vvm_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16mf2(op1,op2,selector,32);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vvm_u16m1(vuint16m1_t op1,vuint16m1_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m1(op1,op2,selector,32);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vvm_u16m2(vuint16m2_t op1,vuint16m2_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m2(op1,op2,selector,32);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vvm_u16m4(vuint16m4_t op1,vuint16m4_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m4(op1,op2,selector,32);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vvm_u16m8(vuint16m8_t op1,vuint16m8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m8(op1,op2,selector,32);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vvm_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32mf2(op1,op2,selector,32);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vvm_u32m1(vuint32m1_t op1,vuint32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m1(op1,op2,selector,32);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vvm_u32m2(vuint32m2_t op1,vuint32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m2(op1,op2,selector,32);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vvm_u32m4(vuint32m4_t op1,vuint32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m4(op1,op2,selector,32);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vvm_u32m8(vuint32m8_t op1,vuint32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m8(op1,op2,selector,32);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vvm_u64m1(vuint64m1_t op1,vuint64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m1(op1,op2,selector,32);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vvm_u64m2(vuint64m2_t op1,vuint64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m2(op1,op2,selector,32);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vvm_u64m4(vuint64m4_t op1,vuint64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m4(op1,op2,selector,32);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vvm_u64m8(vuint64m8_t op1,vuint64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m8(op1,op2,selector,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-1.c
new file mode 100644
index 00000000000..20a7ac99481
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-1.c
@@ -0,0 +1,69 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vfloat32mf2_t test___riscv_vmerge_vvm_f32mf2_tu(vfloat32mf2_t merge,vfloat32mf2_t op1,vfloat32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vfloat32m1_t test___riscv_vmerge_vvm_f32m1_tu(vfloat32m1_t merge,vfloat32m1_t op1,vfloat32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vfloat32m2_t test___riscv_vmerge_vvm_f32m2_tu(vfloat32m2_t merge,vfloat32m2_t op1,vfloat32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vfloat32m4_t test___riscv_vmerge_vvm_f32m4_tu(vfloat32m4_t merge,vfloat32m4_t op1,vfloat32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vfloat32m8_t test___riscv_vmerge_vvm_f32m8_tu(vfloat32m8_t merge,vfloat32m8_t op1,vfloat32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vfloat64m1_t test___riscv_vmerge_vvm_f64m1_tu(vfloat64m1_t merge,vfloat64m1_t op1,vfloat64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vfloat64m2_t test___riscv_vmerge_vvm_f64m2_tu(vfloat64m2_t merge,vfloat64m2_t op1,vfloat64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vfloat64m4_t test___riscv_vmerge_vvm_f64m4_tu(vfloat64m4_t merge,vfloat64m4_t op1,vfloat64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vfloat64m8_t test___riscv_vmerge_vvm_f64m8_tu(vfloat64m8_t merge,vfloat64m8_t op1,vfloat64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-2.c
new file mode 100644
index 00000000000..ac2870c0451
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-2.c
@@ -0,0 +1,69 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vfloat32mf2_t test___riscv_vmerge_vvm_f32mf2_tu(vfloat32mf2_t merge,vfloat32mf2_t op1,vfloat32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vfloat32m1_t test___riscv_vmerge_vvm_f32m1_tu(vfloat32m1_t merge,vfloat32m1_t op1,vfloat32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vfloat32m2_t test___riscv_vmerge_vvm_f32m2_tu(vfloat32m2_t merge,vfloat32m2_t op1,vfloat32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vfloat32m4_t test___riscv_vmerge_vvm_f32m4_tu(vfloat32m4_t merge,vfloat32m4_t op1,vfloat32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vfloat32m8_t test___riscv_vmerge_vvm_f32m8_tu(vfloat32m8_t merge,vfloat32m8_t op1,vfloat32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vfloat64m1_t test___riscv_vmerge_vvm_f64m1_tu(vfloat64m1_t merge,vfloat64m1_t op1,vfloat64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vfloat64m2_t test___riscv_vmerge_vvm_f64m2_tu(vfloat64m2_t merge,vfloat64m2_t op1,vfloat64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vfloat64m4_t test___riscv_vmerge_vvm_f64m4_tu(vfloat64m4_t merge,vfloat64m4_t op1,vfloat64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vfloat64m8_t test___riscv_vmerge_vvm_f64m8_tu(vfloat64m8_t merge,vfloat64m8_t op1,vfloat64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m8_tu(merge,op1,op2,selector,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-3.c
new file mode 100644
index 00000000000..442806f62c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-3.c
@@ -0,0 +1,69 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vfloat32mf2_t test___riscv_vmerge_vvm_f32mf2_tu(vfloat32mf2_t merge,vfloat32mf2_t op1,vfloat32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vfloat32m1_t test___riscv_vmerge_vvm_f32m1_tu(vfloat32m1_t merge,vfloat32m1_t op1,vfloat32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vfloat32m2_t test___riscv_vmerge_vvm_f32m2_tu(vfloat32m2_t merge,vfloat32m2_t op1,vfloat32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vfloat32m4_t test___riscv_vmerge_vvm_f32m4_tu(vfloat32m4_t merge,vfloat32m4_t op1,vfloat32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vfloat32m8_t test___riscv_vmerge_vvm_f32m8_tu(vfloat32m8_t merge,vfloat32m8_t op1,vfloat32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f32m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vfloat64m1_t test___riscv_vmerge_vvm_f64m1_tu(vfloat64m1_t merge,vfloat64m1_t op1,vfloat64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vfloat64m2_t test___riscv_vmerge_vvm_f64m2_tu(vfloat64m2_t merge,vfloat64m2_t op1,vfloat64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vfloat64m4_t test___riscv_vmerge_vvm_f64m4_tu(vfloat64m4_t merge,vfloat64m4_t op1,vfloat64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vfloat64m8_t test___riscv_vmerge_vvm_f64m8_tu(vfloat64m8_t merge,vfloat64m8_t op1,vfloat64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_f64m8_tu(merge,op1,op2,selector,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-4.c
new file mode 100644
index 00000000000..dfa4111913c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-4.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vvm_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vvm_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vvm_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8m1_t test___riscv_vmerge_vvm_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8m2_t test___riscv_vmerge_vvm_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8m4_t test___riscv_vmerge_vvm_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8m8_t test___riscv_vmerge_vvm_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vvm_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16mf4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vvm_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16m1_t test___riscv_vmerge_vvm_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16m2_t test___riscv_vmerge_vvm_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16m4_t test___riscv_vmerge_vvm_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16m8_t test___riscv_vmerge_vvm_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vvm_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32m1_t test___riscv_vmerge_vvm_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32m2_t test___riscv_vmerge_vvm_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32m4_t test___riscv_vmerge_vvm_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32m8_t test___riscv_vmerge_vvm_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint64m1_t test___riscv_vmerge_vvm_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint64m2_t test___riscv_vmerge_vvm_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint64m4_t test___riscv_vmerge_vvm_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint64m8_t test___riscv_vmerge_vvm_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vvm_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vvm_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vvm_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vvm_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vvm_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vvm_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vvm_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vvm_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16mf4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vvm_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vvm_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vvm_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vvm_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vvm_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vvm_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vvm_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vvm_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vvm_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vvm_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vvm_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vvm_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vvm_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vvm_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-5.c
new file mode 100644
index 00000000000..d2e9348d8d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-5.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vvm_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf8_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vvm_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vvm_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8m1_t test___riscv_vmerge_vvm_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8m2_t test___riscv_vmerge_vvm_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8m4_t test___riscv_vmerge_vvm_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8m8_t test___riscv_vmerge_vvm_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vvm_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16mf4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vvm_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16m1_t test___riscv_vmerge_vvm_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16m2_t test___riscv_vmerge_vvm_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16m4_t test___riscv_vmerge_vvm_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16m8_t test___riscv_vmerge_vvm_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vvm_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32m1_t test___riscv_vmerge_vvm_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32m2_t test___riscv_vmerge_vvm_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32m4_t test___riscv_vmerge_vvm_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32m8_t test___riscv_vmerge_vvm_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vint64m1_t test___riscv_vmerge_vvm_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vint64m2_t test___riscv_vmerge_vvm_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint64m4_t test___riscv_vmerge_vvm_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint64m8_t test___riscv_vmerge_vvm_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vvm_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vvm_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vvm_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vvm_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vvm_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vvm_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vvm_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vvm_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16mf4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vvm_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vvm_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vvm_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vvm_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vvm_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vvm_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vvm_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vvm_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vvm_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vvm_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vvm_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vvm_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vvm_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vvm_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m8_tu(merge,op1,op2,selector,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-6.c
new file mode 100644
index 00000000000..a0b8780493f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-6.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vvm_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf8_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vvm_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vvm_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8m1_t test___riscv_vmerge_vvm_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8m2_t test___riscv_vmerge_vvm_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8m4_t test___riscv_vmerge_vvm_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8m8_t test___riscv_vmerge_vvm_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i8m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vvm_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16mf4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vvm_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16m1_t test___riscv_vmerge_vvm_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16m2_t test___riscv_vmerge_vvm_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16m4_t test___riscv_vmerge_vvm_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16m8_t test___riscv_vmerge_vvm_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i16m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vvm_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32m1_t test___riscv_vmerge_vvm_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32m2_t test___riscv_vmerge_vvm_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32m4_t test___riscv_vmerge_vvm_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32m8_t test___riscv_vmerge_vvm_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i32m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vint64m1_t test___riscv_vmerge_vvm_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vint64m2_t test___riscv_vmerge_vvm_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint64m4_t test___riscv_vmerge_vvm_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint64m8_t test___riscv_vmerge_vvm_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_i64m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vvm_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vvm_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vvm_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vvm_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vvm_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vvm_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vvm_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u8m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vvm_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16mf4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vvm_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vvm_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vvm_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vvm_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vvm_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u16m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vvm_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vvm_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vvm_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vvm_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vvm_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u32m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vvm_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vvm_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vvm_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vvm_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vvm_u64m8_tu(merge,op1,op2,selector,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-1.c
new file mode 100644
index 00000000000..15f0c3a45f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-1.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf8(op1,op2,selector,vl);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf4(op1,op2,selector,vl);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf2(op1,op2,selector,vl);
+}
+
+
+vint8m1_t test___riscv_vmerge_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m1(op1,op2,selector,vl);
+}
+
+
+vint8m2_t test___riscv_vmerge_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m2(op1,op2,selector,vl);
+}
+
+
+vint8m4_t test___riscv_vmerge_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m4(op1,op2,selector,vl);
+}
+
+
+vint8m8_t test___riscv_vmerge_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m8(op1,op2,selector,vl);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf4(op1,op2,selector,vl);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf2(op1,op2,selector,vl);
+}
+
+
+vint16m1_t test___riscv_vmerge_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m1(op1,op2,selector,vl);
+}
+
+
+vint16m2_t test___riscv_vmerge_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m2(op1,op2,selector,vl);
+}
+
+
+vint16m4_t test___riscv_vmerge_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m4(op1,op2,selector,vl);
+}
+
+
+vint16m8_t test___riscv_vmerge_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m8(op1,op2,selector,vl);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32mf2(op1,op2,selector,vl);
+}
+
+
+vint32m1_t test___riscv_vmerge_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m1(op1,op2,selector,vl);
+}
+
+
+vint32m2_t test___riscv_vmerge_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m2(op1,op2,selector,vl);
+}
+
+
+vint32m4_t test___riscv_vmerge_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m4(op1,op2,selector,vl);
+}
+
+
+vint32m8_t test___riscv_vmerge_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m8(op1,op2,selector,vl);
+}
+
+
+vint64m1_t test___riscv_vmerge_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m1(op1,op2,selector,vl);
+}
+
+
+vint64m2_t test___riscv_vmerge_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m2(op1,op2,selector,vl);
+}
+
+
+vint64m4_t test___riscv_vmerge_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m4(op1,op2,selector,vl);
+}
+
+
+vint64m8_t test___riscv_vmerge_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m8(op1,op2,selector,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf8(op1,op2,selector,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf4(op1,op2,selector,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf2(op1,op2,selector,vl);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m1(op1,op2,selector,vl);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m2(op1,op2,selector,vl);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m4(op1,op2,selector,vl);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m8(op1,op2,selector,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf4(op1,op2,selector,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf2(op1,op2,selector,vl);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m1(op1,op2,selector,vl);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m2(op1,op2,selector,vl);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m4(op1,op2,selector,vl);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m8(op1,op2,selector,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32mf2(op1,op2,selector,vl);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m1(op1,op2,selector,vl);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m2(op1,op2,selector,vl);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m4(op1,op2,selector,vl);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m8(op1,op2,selector,vl);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m1(op1,op2,selector,vl);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m2(op1,op2,selector,vl);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m4(op1,op2,selector,vl);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m8(op1,op2,selector,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-2.c
new file mode 100644
index 00000000000..7a1db71dec5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-2.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf8(op1,op2,selector,31);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf4(op1,op2,selector,31);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf2(op1,op2,selector,31);
+}
+
+
+vint8m1_t test___riscv_vmerge_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m1(op1,op2,selector,31);
+}
+
+
+vint8m2_t test___riscv_vmerge_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m2(op1,op2,selector,31);
+}
+
+
+vint8m4_t test___riscv_vmerge_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m4(op1,op2,selector,31);
+}
+
+
+vint8m8_t test___riscv_vmerge_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m8(op1,op2,selector,31);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf4(op1,op2,selector,31);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf2(op1,op2,selector,31);
+}
+
+
+vint16m1_t test___riscv_vmerge_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m1(op1,op2,selector,31);
+}
+
+
+vint16m2_t test___riscv_vmerge_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m2(op1,op2,selector,31);
+}
+
+
+vint16m4_t test___riscv_vmerge_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m4(op1,op2,selector,31);
+}
+
+
+vint16m8_t test___riscv_vmerge_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m8(op1,op2,selector,31);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32mf2(op1,op2,selector,31);
+}
+
+
+vint32m1_t test___riscv_vmerge_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m1(op1,op2,selector,31);
+}
+
+
+vint32m2_t test___riscv_vmerge_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m2(op1,op2,selector,31);
+}
+
+
+vint32m4_t test___riscv_vmerge_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m4(op1,op2,selector,31);
+}
+
+
+vint32m8_t test___riscv_vmerge_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m8(op1,op2,selector,31);
+}
+
+
+vint64m1_t test___riscv_vmerge_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m1(op1,op2,selector,31);
+}
+
+
+vint64m2_t test___riscv_vmerge_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m2(op1,op2,selector,31);
+}
+
+
+vint64m4_t test___riscv_vmerge_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m4(op1,op2,selector,31);
+}
+
+
+vint64m8_t test___riscv_vmerge_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m8(op1,op2,selector,31);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf8(op1,op2,selector,31);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf4(op1,op2,selector,31);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf2(op1,op2,selector,31);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m1(op1,op2,selector,31);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m2(op1,op2,selector,31);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m4(op1,op2,selector,31);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m8(op1,op2,selector,31);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf4(op1,op2,selector,31);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf2(op1,op2,selector,31);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m1(op1,op2,selector,31);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m2(op1,op2,selector,31);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m4(op1,op2,selector,31);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m8(op1,op2,selector,31);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32mf2(op1,op2,selector,31);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m1(op1,op2,selector,31);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m2(op1,op2,selector,31);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m4(op1,op2,selector,31);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m8(op1,op2,selector,31);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m1(op1,op2,selector,31);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m2(op1,op2,selector,31);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m4(op1,op2,selector,31);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m8(op1,op2,selector,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-3.c
new file mode 100644
index 00000000000..5b3426d00ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-3.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf8(op1,op2,selector,32);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf4(op1,op2,selector,32);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf2(op1,op2,selector,32);
+}
+
+
+vint8m1_t test___riscv_vmerge_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m1(op1,op2,selector,32);
+}
+
+
+vint8m2_t test___riscv_vmerge_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m2(op1,op2,selector,32);
+}
+
+
+vint8m4_t test___riscv_vmerge_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m4(op1,op2,selector,32);
+}
+
+
+vint8m8_t test___riscv_vmerge_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m8(op1,op2,selector,32);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf4(op1,op2,selector,32);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf2(op1,op2,selector,32);
+}
+
+
+vint16m1_t test___riscv_vmerge_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m1(op1,op2,selector,32);
+}
+
+
+vint16m2_t test___riscv_vmerge_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m2(op1,op2,selector,32);
+}
+
+
+vint16m4_t test___riscv_vmerge_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m4(op1,op2,selector,32);
+}
+
+
+vint16m8_t test___riscv_vmerge_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m8(op1,op2,selector,32);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32mf2(op1,op2,selector,32);
+}
+
+
+vint32m1_t test___riscv_vmerge_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m1(op1,op2,selector,32);
+}
+
+
+vint32m2_t test___riscv_vmerge_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m2(op1,op2,selector,32);
+}
+
+
+vint32m4_t test___riscv_vmerge_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m4(op1,op2,selector,32);
+}
+
+
+vint32m8_t test___riscv_vmerge_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m8(op1,op2,selector,32);
+}
+
+
+vint64m1_t test___riscv_vmerge_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m1(op1,op2,selector,32);
+}
+
+
+vint64m2_t test___riscv_vmerge_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m2(op1,op2,selector,32);
+}
+
+
+vint64m4_t test___riscv_vmerge_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m4(op1,op2,selector,32);
+}
+
+
+vint64m8_t test___riscv_vmerge_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m8(op1,op2,selector,32);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf8(op1,op2,selector,32);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf4(op1,op2,selector,32);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf2(op1,op2,selector,32);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m1(op1,op2,selector,32);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m2(op1,op2,selector,32);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m4(op1,op2,selector,32);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m8(op1,op2,selector,32);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf4(op1,op2,selector,32);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf2(op1,op2,selector,32);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m1(op1,op2,selector,32);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m2(op1,op2,selector,32);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m4(op1,op2,selector,32);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m8(op1,op2,selector,32);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32mf2(op1,op2,selector,32);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m1(op1,op2,selector,32);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m2(op1,op2,selector,32);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m4(op1,op2,selector,32);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m8(op1,op2,selector,32);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m1(op1,op2,selector,32);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m2(op1,op2,selector,32);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m4(op1,op2,selector,32);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m8(op1,op2,selector,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-1.c
new file mode 100644
index 00000000000..6990a3abdde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf8(op1,op2,selector,vl);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf4(op1,op2,selector,vl);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf2(op1,op2,selector,vl);
+}
+
+
+vint8m1_t test___riscv_vmerge_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m1(op1,op2,selector,vl);
+}
+
+
+vint8m2_t test___riscv_vmerge_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m2(op1,op2,selector,vl);
+}
+
+
+vint8m4_t test___riscv_vmerge_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m4(op1,op2,selector,vl);
+}
+
+
+vint8m8_t test___riscv_vmerge_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m8(op1,op2,selector,vl);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf4(op1,op2,selector,vl);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf2(op1,op2,selector,vl);
+}
+
+
+vint16m1_t test___riscv_vmerge_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m1(op1,op2,selector,vl);
+}
+
+
+vint16m2_t test___riscv_vmerge_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m2(op1,op2,selector,vl);
+}
+
+
+vint16m4_t test___riscv_vmerge_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m4(op1,op2,selector,vl);
+}
+
+
+vint16m8_t test___riscv_vmerge_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m8(op1,op2,selector,vl);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32mf2(op1,op2,selector,vl);
+}
+
+
+vint32m1_t test___riscv_vmerge_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m1(op1,op2,selector,vl);
+}
+
+
+vint32m2_t test___riscv_vmerge_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m2(op1,op2,selector,vl);
+}
+
+
+vint32m4_t test___riscv_vmerge_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m4(op1,op2,selector,vl);
+}
+
+
+vint32m8_t test___riscv_vmerge_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m8(op1,op2,selector,vl);
+}
+
+
+vint64m1_t test___riscv_vmerge_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m1(op1,op2,selector,vl);
+}
+
+
+vint64m2_t test___riscv_vmerge_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m2(op1,op2,selector,vl);
+}
+
+
+vint64m4_t test___riscv_vmerge_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m4(op1,op2,selector,vl);
+}
+
+
+vint64m8_t test___riscv_vmerge_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m8(op1,op2,selector,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf8(op1,op2,selector,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf4(op1,op2,selector,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf2(op1,op2,selector,vl);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m1(op1,op2,selector,vl);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m2(op1,op2,selector,vl);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m4(op1,op2,selector,vl);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m8(op1,op2,selector,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf4(op1,op2,selector,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf2(op1,op2,selector,vl);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m1(op1,op2,selector,vl);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m2(op1,op2,selector,vl);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m4(op1,op2,selector,vl);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m8(op1,op2,selector,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32mf2(op1,op2,selector,vl);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m1(op1,op2,selector,vl);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m2(op1,op2,selector,vl);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m4(op1,op2,selector,vl);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m8(op1,op2,selector,vl);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m1(op1,op2,selector,vl);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m2(op1,op2,selector,vl);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m4(op1,op2,selector,vl);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m8(op1,op2,selector,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-2.c
new file mode 100644
index 00000000000..27ec79a3cc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf8(op1,op2,selector,31);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf4(op1,op2,selector,31);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf2(op1,op2,selector,31);
+}
+
+
+vint8m1_t test___riscv_vmerge_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m1(op1,op2,selector,31);
+}
+
+
+vint8m2_t test___riscv_vmerge_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m2(op1,op2,selector,31);
+}
+
+
+vint8m4_t test___riscv_vmerge_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m4(op1,op2,selector,31);
+}
+
+
+vint8m8_t test___riscv_vmerge_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m8(op1,op2,selector,31);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf4(op1,op2,selector,31);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf2(op1,op2,selector,31);
+}
+
+
+vint16m1_t test___riscv_vmerge_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m1(op1,op2,selector,31);
+}
+
+
+vint16m2_t test___riscv_vmerge_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m2(op1,op2,selector,31);
+}
+
+
+vint16m4_t test___riscv_vmerge_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m4(op1,op2,selector,31);
+}
+
+
+vint16m8_t test___riscv_vmerge_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m8(op1,op2,selector,31);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32mf2(op1,op2,selector,31);
+}
+
+
+vint32m1_t test___riscv_vmerge_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m1(op1,op2,selector,31);
+}
+
+
+vint32m2_t test___riscv_vmerge_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m2(op1,op2,selector,31);
+}
+
+
+vint32m4_t test___riscv_vmerge_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m4(op1,op2,selector,31);
+}
+
+
+vint32m8_t test___riscv_vmerge_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m8(op1,op2,selector,31);
+}
+
+
+vint64m1_t test___riscv_vmerge_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m1(op1,op2,selector,31);
+}
+
+
+vint64m2_t test___riscv_vmerge_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m2(op1,op2,selector,31);
+}
+
+
+vint64m4_t test___riscv_vmerge_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m4(op1,op2,selector,31);
+}
+
+
+vint64m8_t test___riscv_vmerge_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m8(op1,op2,selector,31);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf8(op1,op2,selector,31);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf4(op1,op2,selector,31);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf2(op1,op2,selector,31);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m1(op1,op2,selector,31);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m2(op1,op2,selector,31);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m4(op1,op2,selector,31);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m8(op1,op2,selector,31);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf4(op1,op2,selector,31);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf2(op1,op2,selector,31);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m1(op1,op2,selector,31);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m2(op1,op2,selector,31);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m4(op1,op2,selector,31);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m8(op1,op2,selector,31);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32mf2(op1,op2,selector,31);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m1(op1,op2,selector,31);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m2(op1,op2,selector,31);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m4(op1,op2,selector,31);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m8(op1,op2,selector,31);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m1(op1,op2,selector,31);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m2(op1,op2,selector,31);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m4(op1,op2,selector,31);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m8(op1,op2,selector,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-3.c
new file mode 100644
index 00000000000..5a9accaa4ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf8(op1,op2,selector,32);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf4(op1,op2,selector,32);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf2(op1,op2,selector,32);
+}
+
+
+vint8m1_t test___riscv_vmerge_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m1(op1,op2,selector,32);
+}
+
+
+vint8m2_t test___riscv_vmerge_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m2(op1,op2,selector,32);
+}
+
+
+vint8m4_t test___riscv_vmerge_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m4(op1,op2,selector,32);
+}
+
+
+vint8m8_t test___riscv_vmerge_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m8(op1,op2,selector,32);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf4(op1,op2,selector,32);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf2(op1,op2,selector,32);
+}
+
+
+vint16m1_t test___riscv_vmerge_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m1(op1,op2,selector,32);
+}
+
+
+vint16m2_t test___riscv_vmerge_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m2(op1,op2,selector,32);
+}
+
+
+vint16m4_t test___riscv_vmerge_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m4(op1,op2,selector,32);
+}
+
+
+vint16m8_t test___riscv_vmerge_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m8(op1,op2,selector,32);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32mf2(op1,op2,selector,32);
+}
+
+
+vint32m1_t test___riscv_vmerge_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m1(op1,op2,selector,32);
+}
+
+
+vint32m2_t test___riscv_vmerge_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m2(op1,op2,selector,32);
+}
+
+
+vint32m4_t test___riscv_vmerge_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m4(op1,op2,selector,32);
+}
+
+
+vint32m8_t test___riscv_vmerge_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m8(op1,op2,selector,32);
+}
+
+
+vint64m1_t test___riscv_vmerge_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m1(op1,op2,selector,32);
+}
+
+
+vint64m2_t test___riscv_vmerge_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m2(op1,op2,selector,32);
+}
+
+
+vint64m4_t test___riscv_vmerge_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m4(op1,op2,selector,32);
+}
+
+
+vint64m8_t test___riscv_vmerge_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m8(op1,op2,selector,32);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf8(op1,op2,selector,32);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf4(op1,op2,selector,32);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf2(op1,op2,selector,32);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m1(op1,op2,selector,32);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m2(op1,op2,selector,32);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m4(op1,op2,selector,32);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m8(op1,op2,selector,32);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf4(op1,op2,selector,32);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf2(op1,op2,selector,32);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m1(op1,op2,selector,32);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m2(op1,op2,selector,32);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m4(op1,op2,selector,32);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m8(op1,op2,selector,32);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32mf2(op1,op2,selector,32);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m1(op1,op2,selector,32);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m2(op1,op2,selector,32);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m4(op1,op2,selector,32);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m8(op1,op2,selector,32);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m1(op1,op2,selector,32);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m2(op1,op2,selector,32);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m4(op1,op2,selector,32);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m8(op1,op2,selector,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-1.c
new file mode 100644
index 00000000000..a3021804200
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-1.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vxm_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vxm_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vxm_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8m1_t test___riscv_vmerge_vxm_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8m2_t test___riscv_vmerge_vxm_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8m4_t test___riscv_vmerge_vxm_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8m8_t test___riscv_vmerge_vxm_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vxm_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vxm_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16m1_t test___riscv_vmerge_vxm_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16m2_t test___riscv_vmerge_vxm_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16m4_t test___riscv_vmerge_vxm_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16m8_t test___riscv_vmerge_vxm_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vxm_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32m1_t test___riscv_vmerge_vxm_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32m2_t test___riscv_vmerge_vxm_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32m4_t test___riscv_vmerge_vxm_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32m8_t test___riscv_vmerge_vxm_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint64m1_t test___riscv_vmerge_vxm_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint64m2_t test___riscv_vmerge_vxm_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint64m4_t test___riscv_vmerge_vxm_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint64m8_t test___riscv_vmerge_vxm_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vxm_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vxm_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vxm_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vxm_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vxm_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vxm_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vxm_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vxm_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vxm_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vxm_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vxm_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vxm_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vxm_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vxm_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vxm_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vxm_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vxm_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vxm_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vxm_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vxm_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vxm_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vxm_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-2.c
new file mode 100644
index 00000000000..0c63c1fbed0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-2.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vxm_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf8_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vxm_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vxm_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8m1_t test___riscv_vmerge_vxm_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8m2_t test___riscv_vmerge_vxm_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8m4_t test___riscv_vmerge_vxm_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8m8_t test___riscv_vmerge_vxm_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vxm_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vxm_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16m1_t test___riscv_vmerge_vxm_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16m2_t test___riscv_vmerge_vxm_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16m4_t test___riscv_vmerge_vxm_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16m8_t test___riscv_vmerge_vxm_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vxm_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32m1_t test___riscv_vmerge_vxm_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32m2_t test___riscv_vmerge_vxm_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32m4_t test___riscv_vmerge_vxm_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32m8_t test___riscv_vmerge_vxm_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vint64m1_t test___riscv_vmerge_vxm_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vint64m2_t test___riscv_vmerge_vxm_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint64m4_t test___riscv_vmerge_vxm_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint64m8_t test___riscv_vmerge_vxm_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vxm_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vxm_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vxm_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vxm_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vxm_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vxm_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vxm_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vxm_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vxm_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vxm_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vxm_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vxm_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vxm_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vxm_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vxm_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vxm_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vxm_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vxm_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vxm_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vxm_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vxm_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vxm_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m8_tu(merge,op1,op2,selector,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-3.c
new file mode 100644
index 00000000000..25fa997f637
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-3.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vxm_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf8_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vxm_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vxm_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8m1_t test___riscv_vmerge_vxm_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8m2_t test___riscv_vmerge_vxm_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8m4_t test___riscv_vmerge_vxm_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8m8_t test___riscv_vmerge_vxm_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vxm_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vxm_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16m1_t test___riscv_vmerge_vxm_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16m2_t test___riscv_vmerge_vxm_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16m4_t test___riscv_vmerge_vxm_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16m8_t test___riscv_vmerge_vxm_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vxm_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32m1_t test___riscv_vmerge_vxm_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32m2_t test___riscv_vmerge_vxm_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32m4_t test___riscv_vmerge_vxm_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32m8_t test___riscv_vmerge_vxm_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vint64m1_t test___riscv_vmerge_vxm_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vint64m2_t test___riscv_vmerge_vxm_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint64m4_t test___riscv_vmerge_vxm_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint64m8_t test___riscv_vmerge_vxm_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vxm_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vxm_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vxm_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vxm_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vxm_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vxm_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vxm_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vxm_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vxm_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vxm_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vxm_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vxm_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vxm_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vxm_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vxm_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vxm_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vxm_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vxm_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vxm_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vxm_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vxm_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vxm_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m8_tu(merge,op1,op2,selector,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-1.c
new file mode 100644
index 00000000000..0489578f021
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vxm_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vxm_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vxm_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8m1_t test___riscv_vmerge_vxm_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8m2_t test___riscv_vmerge_vxm_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8m4_t test___riscv_vmerge_vxm_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint8m8_t test___riscv_vmerge_vxm_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vxm_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vxm_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16m1_t test___riscv_vmerge_vxm_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16m2_t test___riscv_vmerge_vxm_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16m4_t test___riscv_vmerge_vxm_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint16m8_t test___riscv_vmerge_vxm_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vxm_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32m1_t test___riscv_vmerge_vxm_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32m2_t test___riscv_vmerge_vxm_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32m4_t test___riscv_vmerge_vxm_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint32m8_t test___riscv_vmerge_vxm_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint64m1_t test___riscv_vmerge_vxm_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint64m2_t test___riscv_vmerge_vxm_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint64m4_t test___riscv_vmerge_vxm_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vint64m8_t test___riscv_vmerge_vxm_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vxm_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vxm_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vxm_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vxm_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vxm_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vxm_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vxm_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vxm_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vxm_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vxm_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vxm_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vxm_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vxm_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vxm_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32mf2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vxm_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vxm_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vxm_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vxm_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vxm_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m1_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vxm_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m2_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vxm_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m4_tu(merge,op1,op2,selector,vl);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vxm_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m8_tu(merge,op1,op2,selector,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-2.c
new file mode 100644
index 00000000000..a2ac7d69bf2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vxm_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf8_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vxm_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vxm_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8m1_t test___riscv_vmerge_vxm_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8m2_t test___riscv_vmerge_vxm_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8m4_t test___riscv_vmerge_vxm_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint8m8_t test___riscv_vmerge_vxm_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vxm_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vxm_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16m1_t test___riscv_vmerge_vxm_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16m2_t test___riscv_vmerge_vxm_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16m4_t test___riscv_vmerge_vxm_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint16m8_t test___riscv_vmerge_vxm_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vxm_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32m1_t test___riscv_vmerge_vxm_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32m2_t test___riscv_vmerge_vxm_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32m4_t test___riscv_vmerge_vxm_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint32m8_t test___riscv_vmerge_vxm_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vint64m1_t test___riscv_vmerge_vxm_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vint64m2_t test___riscv_vmerge_vxm_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vint64m4_t test___riscv_vmerge_vxm_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vint64m8_t test___riscv_vmerge_vxm_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vxm_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vxm_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vxm_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vxm_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vxm_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vxm_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vxm_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vxm_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vxm_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vxm_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vxm_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vxm_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vxm_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vxm_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32mf2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vxm_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vxm_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vxm_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vxm_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m8_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vxm_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m1_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vxm_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m2_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vxm_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m4_tu(merge,op1,op2,selector,31);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vxm_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m8_tu(merge,op1,op2,selector,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-3.c
new file mode 100644
index 00000000000..f1df0e40da5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmerge_vxm_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf8_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8mf4_t test___riscv_vmerge_vxm_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8mf2_t test___riscv_vmerge_vxm_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8m1_t test___riscv_vmerge_vxm_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8m2_t test___riscv_vmerge_vxm_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8m4_t test___riscv_vmerge_vxm_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint8m8_t test___riscv_vmerge_vxm_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i8m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16mf4_t test___riscv_vmerge_vxm_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16mf2_t test___riscv_vmerge_vxm_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16m1_t test___riscv_vmerge_vxm_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16m2_t test___riscv_vmerge_vxm_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16m4_t test___riscv_vmerge_vxm_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint16m8_t test___riscv_vmerge_vxm_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i16m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32mf2_t test___riscv_vmerge_vxm_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32m1_t test___riscv_vmerge_vxm_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32m2_t test___riscv_vmerge_vxm_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32m4_t test___riscv_vmerge_vxm_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint32m8_t test___riscv_vmerge_vxm_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i32m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vint64m1_t test___riscv_vmerge_vxm_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vint64m2_t test___riscv_vmerge_vxm_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vint64m4_t test___riscv_vmerge_vxm_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vint64m8_t test___riscv_vmerge_vxm_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_i64m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8mf8_t test___riscv_vmerge_vxm_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8mf4_t test___riscv_vmerge_vxm_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8mf2_t test___riscv_vmerge_vxm_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8m1_t test___riscv_vmerge_vxm_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8m2_t test___riscv_vmerge_vxm_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8m4_t test___riscv_vmerge_vxm_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint8m8_t test___riscv_vmerge_vxm_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,vbool1_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u8m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16mf4_t test___riscv_vmerge_vxm_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16mf2_t test___riscv_vmerge_vxm_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16m1_t test___riscv_vmerge_vxm_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16m2_t test___riscv_vmerge_vxm_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16m4_t test___riscv_vmerge_vxm_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint16m8_t test___riscv_vmerge_vxm_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,vbool2_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u16m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32mf2_t test___riscv_vmerge_vxm_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32mf2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32m1_t test___riscv_vmerge_vxm_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32m2_t test___riscv_vmerge_vxm_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32m4_t test___riscv_vmerge_vxm_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint32m8_t test___riscv_vmerge_vxm_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,vbool4_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u32m8_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint64m1_t test___riscv_vmerge_vxm_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,vbool64_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m1_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint64m2_t test___riscv_vmerge_vxm_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,vbool32_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m2_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint64m4_t test___riscv_vmerge_vxm_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,vbool16_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m4_tu(merge,op1,op2,selector,32);
+}
+
+
+vuint64m8_t test___riscv_vmerge_vxm_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,vbool8_t selector,size_t vl)
+{
+    return __riscv_vmerge_vxm_u64m8_tu(merge,op1,op2,selector,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmerge\.vxm\s+v[0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */