[gcc r13-6117] simplify-rtx: Fix VOIDmode operand handling in simplify_subreg [PR108805]

[gcc r13-6117] simplify-rtx: Fix VOIDmode operand handling in simplify_subreg [PR108805]

[Uros Bizjak]

https://gcc.gnu.org/g:6ac3ebed5ffbac0d81c5a1d0cb1e345cfad202a8

commit r13-6117-g6ac3ebed5ffbac0d81c5a1d0cb1e345cfad202a8
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Fri Feb 17 15:58:12 2023 +0100

    simplify-rtx: Fix VOIDmode operand handling in simplify_subreg [PR108805]
    
    simplify_subreg can return VOIDmode const_int operand and will
    cause ICE in simplify_gen_subreg when this operand is passed to it.
    
    The patch uses int_outermode instead of GET_MODE of temporary as the
    innermode argument of simplify_gen_subreg.
    
    2023-02-17  Uroš Bizjak  <ubizjak@gmail.com>
    
    gcc/ChangeLog:
    
            PR target/108805
            * simplify-rtx.cc (simplify_context::simplify_subreg): Use
            int_outermode instead of GET_MODE (tem) to prevent
            VOIDmode from entering simplify_gen_subreg.
    
    gcc/testsuite/ChangeLog:
    
            PR target/108805
            * gcc.dg/pr108805.c: New test.

Diff:
---
 gcc/simplify-rtx.cc             |  2 +-
 gcc/testsuite/gcc.dg/pr108805.c | 20 ++++++++++++++++++++
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
index 0a1dd88b0a8..3955929bb70 100644
--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
@@ -7665,7 +7665,7 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
     {
       rtx tem = simplify_subreg (int_outermode, op, innermode, byte);
       if (tem)
-	return simplify_gen_subreg (outermode, tem, GET_MODE (tem), 0);
+	return simplify_gen_subreg (outermode, tem, int_outermode, 0);
     }
 
   /* If OP is a vector comparison and the subreg is not changing the
diff --git a/gcc/testsuite/gcc.dg/pr108805.c b/gcc/testsuite/gcc.dg/pr108805.c
new file mode 100644
index 00000000000..280d3f5c377
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr108805.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target longlong64 } } */
+/* { dg-options "-O" } */
+/* { dg-additional-options "-msse2" { target x86_64-*-* i?86-*-* } } */
+
+typedef __INT8_TYPE__ __attribute__((__vector_size__ (4))) U;
+typedef __INT32_TYPE__ __attribute__((__vector_size__ (4))) V;
+typedef __UINT64_TYPE__ __attribute__((__vector_size__ (8))) W;
+
+int i;
+U h;
+W g;
+
+U
+foo (void)
+{
+  W w = i != g;
+  V v = __builtin_convertvector (i | w >> 2, V);
+  U u = (U) v[0] + h;
+  return u;
+}