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* [gcc r13-6686] riscv: thead: Add support for the XTheadCondMov ISA extensions
@ 2023-03-15 9:02 Philipp Tomsich
0 siblings, 0 replies; only message in thread
From: Philipp Tomsich @ 2023-03-15 9:02 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8e7ffe126debfbc59e2d359ef3c37899327e2055
commit r13-6686-g8e7ffe126debfbc59e2d359ef3c37899327e2055
Author: Christoph Müllner <christoph.muellner@vrull.eu>
Date: Mon Aug 8 17:48:20 2022 +0200
riscv: thead: Add support for the XTheadCondMov ISA extensions
This patch adds support for XTheadCondMov ISA extension.
The extension brings a one-sided conditional move (no else-assignment).
Given that GCC has a great if-conversion pass, we don't need to do much,
besides properly expanding mov<mode>cc accordingly and adjust the cost
model.
gcc/ChangeLog:
* config/riscv/iterators.md (TARGET_64BIT): Add GPR2 iterator.
* config/riscv/riscv-protos.h (riscv_expand_conditional_move):
Add prototype.
* config/riscv/riscv.cc (riscv_rtx_costs): Add costs for
XTheadCondMov.
(riscv_expand_conditional_move): New function.
(riscv_expand_conditional_move_onesided): New function.
* config/riscv/riscv.md: Add support for XTheadCondMov.
* config/riscv/thead.md (*th_cond_mov<GPR:mode><GPR2:mode>): Add
support for XTheadCondMov.
(*th_cond_gpr_mov<GPR:mode><GPR2:mode>): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c: New test.
* gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c: New test.
* gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c: New test.
* gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c: New test.
* gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c: New test.
* gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c: New test.
* gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c: New test.
* gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c: New test.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diff:
---
gcc/config/riscv/iterators.md | 4 +
gcc/config/riscv/riscv-protos.h | 2 +-
gcc/config/riscv/riscv.cc | 100 ++++++++++++++++++---
gcc/config/riscv/riscv.md | 17 ++--
gcc/config/riscv/thead.md | 37 ++++++++
.../gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c | 38 ++++++++
.../gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c | 38 ++++++++
.../gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c | 38 ++++++++
.../gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c | 38 ++++++++
.../riscv/xtheadcondmov-mvnez-imm-cond.c | 38 ++++++++
.../gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c | 38 ++++++++
.../riscv/xtheadcondmov-mvnez-reg-cond.c | 38 ++++++++
.../gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c | 38 ++++++++
13 files changed, 440 insertions(+), 24 deletions(-)
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 5b70ab20758..9b767038452 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -26,6 +26,10 @@
;; from the same template.
(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
+;; A copy of GPR that can be used when a pattern has two independent
+;; modes.
+(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
+
;; This mode iterator allows :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index f35aaf35b48..ac70d9c841a 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -58,8 +58,8 @@ extern const char *riscv_output_return ();
extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
-extern void riscv_expand_conditional_move (rtx, rtx, rtx, rtx_code, rtx, rtx);
#endif
+extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx);
extern rtx riscv_legitimize_call_address (rtx);
extern void riscv_set_return_address (rtx, rtx);
extern bool riscv_expand_block_move (rtx, rtx, rtx);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 217f4070092..f5d83d72efa 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2312,8 +2312,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
return false;
case IF_THEN_ELSE:
- if (TARGET_SFB_ALU
- && register_operand (XEXP (x, 1), mode)
+ if ((TARGET_SFB_ALU || TARGET_XTHEADCONDMOV)
+ && reg_or_0_operand (XEXP (x, 1), mode)
&& sfb_alu_operand (XEXP (x, 2), mode)
&& comparison_operator (XEXP (x, 0), VOIDmode))
{
@@ -3111,13 +3111,30 @@ riscv_extend_comparands (rtx_code code, rtx *op0, rtx *op1)
}
}
-/* Convert a comparison into something that can be used in a branch. On
- entry, *OP0 and *OP1 are the values being compared and *CODE is the code
- used to compare them. Update them to describe the final comparison. */
+/* Convert a comparison into something that can be used in a branch or
+ conditional move. On entry, *OP0 and *OP1 are the values being
+ compared and *CODE is the code used to compare them.
+
+ Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
+ If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are
+ emitted. */
static void
-riscv_emit_int_compare (enum rtx_code *code, rtx *op0, rtx *op1)
+riscv_emit_int_compare (enum rtx_code *code, rtx *op0, rtx *op1,
+ bool need_eq_ne_p = false)
{
+ if (need_eq_ne_p)
+ {
+ rtx cmp_op0 = *op0;
+ rtx cmp_op1 = *op1;
+ if (*code == EQ || *code == NE)
+ {
+ *op0 = riscv_zero_if_equal (cmp_op0, cmp_op1);
+ *op1 = const0_rtx;
+ return;
+ }
+ }
+
if (splittable_const_int_operand (*op1, VOIDmode))
{
HOST_WIDE_INT rhs = INTVAL (*op1);
@@ -3303,16 +3320,71 @@ riscv_expand_conditional_branch (rtx label, rtx_code code, rtx op0, rtx op1)
emit_jump_insn (gen_condjump (condition, label));
}
-/* If (CODE OP0 OP1) holds, move CONS to DEST; else move ALT to DEST. */
+/* Helper to emit two one-sided conditional moves for the movecc. */
-void
-riscv_expand_conditional_move (rtx dest, rtx cons, rtx alt, rtx_code code,
- rtx op0, rtx op1)
+static void
+riscv_expand_conditional_move_onesided (rtx dest, rtx cons, rtx alt,
+ rtx_code code, rtx op0, rtx op1)
{
- riscv_emit_int_compare (&code, &op0, &op1);
- rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
- emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest), cond,
- cons, alt)));
+ machine_mode mode = GET_MODE (dest);
+
+ gcc_assert (GET_MODE_CLASS (mode) == MODE_INT);
+ gcc_assert (reg_or_0_operand (cons, mode));
+ gcc_assert (reg_or_0_operand (alt, mode));
+
+ riscv_emit_int_compare (&code, &op0, &op1, true);
+ rtx cond = gen_rtx_fmt_ee (code, mode, op0, op1);
+
+ rtx tmp1 = gen_reg_rtx (mode);
+ rtx tmp2 = gen_reg_rtx (mode);
+
+ emit_insn (gen_rtx_SET (tmp1, gen_rtx_IF_THEN_ELSE (mode, cond,
+ cons, const0_rtx)));
+
+ /* We need to expand a sequence for both blocks and we do that such,
+ that the second conditional move will use the inverted condition.
+ We use temporaries that are or'd to the dest register. */
+ cond = gen_rtx_fmt_ee ((code == EQ) ? NE : EQ, mode, op0, op1);
+ emit_insn (gen_rtx_SET (tmp2, gen_rtx_IF_THEN_ELSE (mode, cond,
+ alt, const0_rtx)));
+
+ emit_insn (gen_rtx_SET (dest, gen_rtx_IOR (mode, tmp1, tmp2)));
+ }
+
+/* Emit a cond move: If OP holds, move CONS to DEST; else move ALT to DEST.
+ Return 0 if expansion failed. */
+
+bool
+riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
+{
+ machine_mode mode = GET_MODE (dest);
+ rtx_code code = GET_CODE (op);
+ rtx op0 = XEXP (op, 0);
+ rtx op1 = XEXP (op, 1);
+
+ if (TARGET_XTHEADCONDMOV
+ && GET_MODE_CLASS (mode) == MODE_INT
+ && reg_or_0_operand (cons, mode)
+ && reg_or_0_operand (alt, mode)
+ && GET_MODE (op) == mode
+ && GET_MODE (op0) == mode
+ && GET_MODE (op1) == mode
+ && (code == EQ || code == NE))
+ {
+ riscv_expand_conditional_move_onesided (dest, cons, alt, code, op0, op1);
+ return true;
+ }
+ else if (TARGET_SFB_ALU
+ && mode == word_mode)
+ {
+ riscv_emit_int_compare (&code, &op0, &op1);
+ rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+ emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
+ cond, cons, alt)));
+ return true;
+ }
+
+ return false;
}
/* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c53c1a7609e..34d4a20dcf4 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -242,6 +242,7 @@
;; bitmanip bit manipulation instructions
;; rotate rotation instructions
;; atomic atomic instructions
+;; condmove conditional moves
;; crypto cryptography instructions
;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
;; rdvlenb vector byte length vlenb csrr read
@@ -339,7 +340,7 @@
"unknown,branch,jump,call,load,fpload,store,fpstore,
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
- atomic,crypto,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
+ atomic,condmove,crypto,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,
vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,
@@ -2317,17 +2318,15 @@
(define_expand "mov<mode>cc"
[(set (match_operand:GPR 0 "register_operand")
(if_then_else:GPR (match_operand 1 "comparison_operator")
- (match_operand:GPR 2 "register_operand")
+ (match_operand:GPR 2 "reg_or_0_operand")
(match_operand:GPR 3 "sfb_alu_operand")))]
- "TARGET_SFB_ALU"
+ "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV"
{
- rtx cmp = operands[1];
- /* We only handle word mode integer compares for now. */
- if (GET_MODE (XEXP (cmp, 0)) != word_mode)
+ if (riscv_expand_conditional_move (operands[0], operands[1],
+ operands[2], operands[3]))
+ DONE;
+ else
FAIL;
- riscv_expand_conditional_move (operands[0], operands[2], operands[3],
- GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1));
- DONE;
})
(define_insn "*mov<GPR:mode><X:mode>cc"
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 372d4603543..88b6a95e993 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -101,3 +101,40 @@
"TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
"th.tst\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
+
+;; XTheadCondMov
+
+(define_insn "*th_cond_mov<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r")
+ (if_then_else:GPR
+ (match_operator 4 "equality_operator"
+ [(match_operand:GPR2 1 "register_operand" "r,r")
+ (const_int 0)])
+ (match_operand:GPR 2 "reg_or_0_operand" "rJ,0")
+ (match_operand:GPR 3 "reg_or_0_operand" "0,rJ")))]
+ "TARGET_XTHEADCONDMOV"
+{
+ if (which_alternative == 0)
+ return "th.mv%C4z\t%0,%z2,%1";
+
+ /* Invert the condition and take else-block. */
+ rtx_code code = GET_CODE (operands[4]);
+ code = (code == EQ) ? NE : EQ;
+ operands[4] = gen_rtx_fmt_ee (code, VOIDmode, const0_rtx, const0_rtx);
+ return "th.mv%C4z\t%0,%z3,%1";
+}
+ [(set_attr "type" "condmove")
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn "*th_cond_gpr_mov<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r")
+ (if_then_else:GPR
+ (match_operand:GPR2 1 "register_operand" "r,r")
+ (match_operand:GPR 2 "reg_or_0_operand" "rJ,0")
+ (match_operand:GPR 3 "reg_or_0_operand" "0,rJ")))]
+ "TARGET_XTHEADCONDMOV"
+ "@
+ th.mvnez\t%0,%z2,%1
+ th.mveqz\t%0,%z3,%1"
+ [(set_attr "type" "condmove")
+ (set_attr "mode" "<GPR:MODE>")])
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c
new file mode 100644
index 00000000000..913ae43f21b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond)
+{
+ if (cond == 0)
+ return 1025;
+ return x;
+}
+
+long
+not_long_int (long x, int cond)
+{
+ if (cond == 0)
+ return 1025l;
+ return x;
+}
+
+int
+not_int_long (int x, long cond)
+{
+ if (cond == 0)
+ return 1025;
+ return x;
+}
+
+long
+not_long_long (long x, int cond)
+{
+ if (cond == 0)
+ return 1025l;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mveqz" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c
new file mode 100644
index 00000000000..1bc8b838233
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond)
+{
+ if (!cond)
+ return 1025;
+ return x;
+}
+
+long
+not_long_int (long x, int cond)
+{
+ if (!cond)
+ return 1025l;
+ return x;
+}
+
+int
+not_int_long (int x, long cond)
+{
+ if (!cond)
+ return 1025;
+ return x;
+}
+
+long
+not_long_long (long x, int cond)
+{
+ if (!cond)
+ return 1025l;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mveqz" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c
new file mode 100644
index 00000000000..8ef5869a89b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond, int v)
+{
+ if (cond == 0)
+ return v;
+ return x;
+}
+
+long
+not_long_int (long x, int cond, long v)
+{
+ if (cond == 0)
+ return v;
+ return x;
+}
+
+int
+not_int_long (int x, long cond, int v)
+{
+ if (cond == 0)
+ return v;
+ return x;
+}
+
+long
+not_long_long (long x, int cond, long v)
+{
+ if (cond == 0)
+ return v;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mveqz" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c
new file mode 100644
index 00000000000..f9568bee27f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond, int v)
+{
+ if (!cond)
+ return v;
+ return x;
+}
+
+long
+not_long_int (long x, int cond, long v)
+{
+ if (!cond)
+ return v;
+ return x;
+}
+
+int
+not_int_long (int x, long cond, int v)
+{
+ if (!cond)
+ return v;
+ return x;
+}
+
+long
+not_long_long (long x, int cond, long v)
+{
+ if (!cond)
+ return v;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mveqz" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c
new file mode 100644
index 00000000000..8feddbeb79d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond)
+{
+ if (cond)
+ return 1025;
+ return x;
+}
+
+long
+not_long_int (long x, int cond)
+{
+ if (cond)
+ return 1025l;
+ return x;
+}
+
+int
+not_int_long (int x, long cond)
+{
+ if (cond)
+ return 1025;
+ return x;
+}
+
+long
+not_long_long (long x, int cond)
+{
+ if (cond)
+ return 1025l;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mvnez" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c
new file mode 100644
index 00000000000..7c08e20c25d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond)
+{
+ if (cond != 0)
+ return 1025;
+ return x;
+}
+
+long
+not_long_int (long x, int cond)
+{
+ if (cond != 0)
+ return 1025l;
+ return x;
+}
+
+int
+not_int_long (int x, long cond)
+{
+ if (cond != 0)
+ return 1025;
+ return x;
+}
+
+long
+not_long_long (long x, int cond)
+{
+ if (cond != 0)
+ return 1025l;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mvnez" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c
new file mode 100644
index 00000000000..c1619509af9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond, int v)
+{
+ if (cond)
+ return v;
+ return x;
+}
+
+long
+not_long_int (long x, int cond, long v)
+{
+ if (cond)
+ return v;
+ return x;
+}
+
+int
+not_int_long (int x, long cond, int v)
+{
+ if (cond)
+ return v;
+ return x;
+}
+
+long
+not_long_long (long x, int cond, long v)
+{
+ if (cond)
+ return v;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mvnez" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c
new file mode 100644
index 00000000000..ff95a57927a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond, int v)
+{
+ if (cond != 0)
+ return v;
+ return x;
+}
+
+long
+not_long_int (long x, int cond, long v)
+{
+ if (cond != 0)
+ return v;
+ return x;
+}
+
+int
+not_int_long (int x, long cond, int v)
+{
+ if (cond != 0)
+ return v;
+ return x;
+}
+
+long
+not_long_long (long x, int cond, long v)
+{
+ if (cond != 0)
+ return v;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mvnez" 4 } } */
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2023-03-15 9:02 [gcc r13-6686] riscv: thead: Add support for the XTheadCondMov ISA extensions Philipp Tomsich
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