[gcc r13-6703] Daily bump.

[gcc r13-6703] Daily bump.

[GCC Administrator]

https://gcc.gnu.org/g:39b1814c02724d7390e7cc7197b552711f09c494

commit r13-6703-g39b1814c02724d7390e7cc7197b552711f09c494
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Mar 16 00:16:56 2023 +0000

    Daily bump.

Diff:
---
 gcc/ChangeLog           | 209 ++++++++++++++++++++++++++++++++++++++++++++++++
 gcc/DATESTAMP           |   2 +-
 gcc/cp/ChangeLog        |  35 ++++++++
 gcc/fortran/ChangeLog   |   7 ++
 gcc/m2/ChangeLog        |   6 ++
 gcc/testsuite/ChangeLog | 128 +++++++++++++++++++++++++++++
 libgm2/ChangeLog        |   8 ++
 7 files changed, 394 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7d899563450..76e5dca4260 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,212 @@
+2023-03-15  David Malcolm  <dmalcolm@redhat.com>
+
+	PR analyzer/109097
+	* diagnostic-format-sarif.cc (class sarif_invocation): New.
+	(class sarif_ice_notification): New.
+	(sarif_builder::m_invocation_obj): New field.
+	(sarif_invocation::add_notification_for_ice): New.
+	(sarif_invocation::prepare_to_flush): New.
+	(sarif_ice_notification::sarif_ice_notification): New.
+	(sarif_builder::sarif_builder): Add m_invocation_obj.
+	(sarif_builder::end_diagnostic): Special-case DK_ICE and
+	DK_ICE_NOBT.
+	(sarif_builder::flush_to_file): Call prepare_to_flush on
+	m_invocation_obj.  Pass the latter to make_top_level_object.
+	(sarif_builder::make_result_object): Move creation of "locations"
+	array to...
+	(sarif_builder::make_locations_arr): ...this new function.
+	(sarif_builder::make_top_level_object): Add "invocation_obj" param
+	and pass it to make_run_object.
+	(sarif_builder::make_run_object): Add "invocation_obj" param and
+	use it.
+	(sarif_ice_handler): New callback.
+	(diagnostic_output_format_init_sarif): Wire up sarif_ice_handler.
+	* diagnostic.cc (diagnostic_initialize): Initialize new field
+	"ice_handler_cb".
+	(diagnostic_action_after_output): If it is set, make one attempt
+	to call ice_handler_cb.
+	* diagnostic.h (diagnostic_context::ice_handler_cb): New field.
+
+2023-03-15  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386-expand.cc (expand_vec_perm_blend):
+	Handle 8-byte modes only with TARGET_MMX_WITH_SSE. Handle V2SFmode
+	and fix V2HImode handling.
+	(expand_vec_perm_1): Try to emit BLEND instruction
+	before MOVSS/MOVSD.
+	* config/i386/mmx.md (*mmx_blendps): New insn pattern.
+
+2023-03-15  Tobias Burnus  <tobias@codesourcery.com>
+
+	* omp-low.cc (omp_runtime_api_call): Add omp_in_explicit_task.
+
+2023-03-15  Richard Biener  <rguenther@suse.de>
+
+	* gimple-ssa-warn-access.cc (pass_waccess::check_pointer_uses):
+	Do not diagnose clobbers.
+
+2023-03-15  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/109139
+	* tree-ssa-live.cc (remove_unused_locals): Look at the
+	base address for unused decls on the LHS of .DEFERRED_INIT.
+
+2023-03-15  Xi Ruoyao  <xry111@xry111.site>
+
+	PR other/109086
+	* builtins.cc (inline_string_cmp): Force the character
+	difference into "result" pseudo-register, instead of reassign
+	the pseudo-register.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* config.gcc: Add thead.o to RISC-V extra_objs.
+	* config/riscv/peephole.md: Add mempair peephole passes.
+	* config/riscv/riscv-protos.h (riscv_split_64bit_move_p): New
+	prototype.
+	(th_mempair_operands_p): Likewise.
+	(th_mempair_order_operands): Likewise.
+	(th_mempair_prepare_save_restore_operands): Likewise.
+	(th_mempair_save_restore_regs): Likewise.
+	(th_mempair_output_move): Likewise.
+	* config/riscv/riscv.cc (riscv_save_reg): Move code.
+	(riscv_restore_reg): Move code.
+	(riscv_for_each_saved_reg): Add code to emit mempair insns.
+	* config/riscv/t-riscv: Add thead.cc.
+	* config/riscv/thead.md (*th_mempair_load_<GPR:mode>2):
+	New insn.
+	(*th_mempair_store_<GPR:mode>2): Likewise.
+	(*th_mempair_load_extendsidi2): Likewise.
+	(*th_mempair_load_zero_extendsidi2): Likewise.
+	* config/riscv/thead.cc: New file.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* config/riscv/constraints.md (TARGET_XTHEADFMV ? FP_REGS : NO_REGS)
+	New constraint "th_f_fmv".
+	(TARGET_XTHEADFMV ? GR_REGS : NO_REGS): New constraint
+	"th_r_fmv".
+	* config/riscv/riscv.cc (riscv_split_doubleword_move):
+	Add split code for XTheadFmv.
+	(riscv_secondary_memory_needed): XTheadFmv does not need
+	secondary memory.
+	* config/riscv/riscv.md: Add new UNSPEC_XTHEADFMV and
+	UNSPEC_XTHEADFMV_HW. Add support for XTheadFmv to
+	movdf_hardfloat_rv32.
+	* config/riscv/thead.md (th_fmv_hw_w_x): New INSN.
+	(th_fmv_x_w): New INSN.
+	(th_fmv_x_hw): New INSN.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* config/riscv/riscv.md (maddhisi4): New expand.
+	(msubhisi4): New expand.
+	* config/riscv/thead.md (*th_mula<mode>): New pattern.
+	(*th_mulawsi): New pattern.
+	(*th_mulawsi2): New pattern.
+	(*th_maddhisi4): New pattern.
+	(*th_sextw_maddhisi4): New pattern.
+	(*th_muls<mode>): New pattern.
+	(*th_mulswsi): New pattern.
+	(*th_mulswsi2): New pattern.
+	(*th_msubhisi4): New pattern.
+	(*th_sextw_msubhisi4): New pattern.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* config/riscv/iterators.md (TARGET_64BIT): Add GPR2 iterator.
+	* config/riscv/riscv-protos.h (riscv_expand_conditional_move):
+	Add prototype.
+	* config/riscv/riscv.cc (riscv_rtx_costs): Add costs for
+	XTheadCondMov.
+	(riscv_expand_conditional_move): New function.
+	(riscv_expand_conditional_move_onesided): New function.
+	* config/riscv/riscv.md: Add support for XTheadCondMov.
+	* config/riscv/thead.md (*th_cond_mov<GPR:mode><GPR2:mode>): Add
+	support for XTheadCondMov.
+	(*th_cond_gpr_mov<GPR:mode><GPR2:mode>): Likewise.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* config/riscv/bitmanip.md (clzdi2): New expand.
+	(clzsi2): New expand.
+	(ctz<mode>2): New expand.
+	(popcount<mode>2): New expand.
+	(<bitmanip_optab>si2): Rename INSN.
+	(*<bitmanip_optab>si2): Hide INSN name.
+	(<bitmanip_optab>di2): Rename INSN.
+	(*<bitmanip_optab>di2): Hide INSN name.
+	(rotrsi3): Remove INSN.
+	(rotr<mode>3): Add expand.
+	(*rotrsi3): New INSN.
+	(rotrdi3): Rename INSN.
+	(*rotrdi3): Hide INSN name.
+	(rotrsi3_sext): Rename INSN.
+	(*rotrsi3_sext): Hide INSN name.
+	(bswap<mode>2): Remove INSN.
+	(bswapdi2): Add expand.
+	(bswapsi2): Add expand.
+	(*bswap<mode>2): Hide INSN name.
+	* config/riscv/riscv.cc (riscv_rtx_costs): Add costs for sign
+	extraction.
+	* config/riscv/riscv.md (extv<mode>): New expand.
+	(extzv<mode>): New expand.
+	* config/riscv/thead.md (*th_srri<mode>3): New INSN.
+	(*th_ext<mode>): New INSN.
+	(*th_extu<mode>): New INSN.
+	(*th_clz<mode>2): New INSN.
+	(*th_rev<mode>2): New INSN.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* config/riscv/riscv.cc (riscv_rtx_costs): Add xthead:tst cost.
+	* config/riscv/thead.md (*th_tst<mode>3): New INSN.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* config/riscv/riscv.md: Include thead.md
+	* config/riscv/thead.md: New file.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906".
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* common/config/riscv/riscv-common.cc: Add xthead* extensions.
+	* config/riscv/riscv-opts.h (MASK_XTHEADBA): New.
+	(MASK_XTHEADBB): New.
+	(MASK_XTHEADBS): New.
+	(MASK_XTHEADCMO): New.
+	(MASK_XTHEADCONDMOV): New.
+	(MASK_XTHEADFMEMIDX): New.
+	(MASK_XTHEADFMV): New.
+	(MASK_XTHEADINT): New.
+	(MASK_XTHEADMAC): New.
+	(MASK_XTHEADMEMIDX): New.
+	(MASK_XTHEADMEMPAIR): New.
+	(MASK_XTHEADSYNC): New.
+	(TARGET_XTHEADBA): New.
+	(TARGET_XTHEADBB): New.
+	(TARGET_XTHEADBS): New.
+	(TARGET_XTHEADCMO): New.
+	(TARGET_XTHEADCONDMOV): New.
+	(TARGET_XTHEADFMEMIDX): New.
+	(TARGET_XTHEADFMV): New.
+	(TARGET_XTHEADINT): New.
+	(TARGET_XTHEADMAC): New.
+	(TARGET_XTHEADMEMIDX): New.
+	(TARGET_XTHEADMEMPAIR): new.
+	(TARGET_XTHEADSYNC): New.
+	* config/riscv/riscv.opt: Add riscv_xthead_subext.
+
+2023-03-15  Hu, Lin1  <lin1.hu@intel.com>
+
+	PR target/109117
+	* config/i386/i386-builtin.def (__builtin_ia32_vaesdec_v16qi,
+	__builtin_ia32_vaesdeclast_v16qi,__builtin_ia32_vaesenc_v16qi,
+	__builtin_ia32_vaesenclast_v16qi): Require OPTION_MASK_ISA_AVX512VL.
+
 2023-03-14  Jakub Jelinek  <jakub@redhat.com>
 
 	PR target/109109
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1541514c486..b0f638be23e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230315
+20230316
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index b9231ad68f4..a9f3f61d494 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,38 @@
+2023-03-15  Jason Merrill  <jason@redhat.com>
+
+	PR c++/103871
+	PR c++/98056
+	* typeck.cc (cp_build_modify_expr): Allow array initialization of
+	DECL_ARTIFICIAL variable.
+
+2023-03-15  Marek Polacek  <polacek@redhat.com>
+
+	PR c++/107280
+	* constexpr.cc (cxx_eval_store_expression): Strip location wrappers.
+
+2023-03-15  Jason Merrill  <jason@redhat.com>
+
+	PR c++/58538
+	* semantics.cc (check_template_template_default_arg): Check
+	maybe_get_template_decl_from_type_decl.
+
+2023-03-15  Jason Merrill  <jason@redhat.com>
+
+	PR c++/108179
+	PR c++/104107
+	PR c++/95036
+	* pt.cc (coerce_template_template_parms): Use args from
+	DECL_CONTEXT (arg_tmpl) instead of outer_args.
+
+2023-03-15  Jason Merrill  <jason@redhat.com>
+
+	PR c++/108179
+	* pt.cc	(coerce_template_template_parms): Take the arg and parm
+	templates directly.
+	(coerce_template_template_parm): Adjust.
+	(template_template_parm_bindings_ok_p): Adjust.
+	(convert_template_argument): Adjust.
+
 2023-03-14  Patrick Palka  <ppalka@redhat.com>
 
 	PR c++/96830
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 5679d29dad9..22d3de49b85 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,10 @@
+2023-03-15  Harald Anlauf  <anlauf@gmx.de>
+	    Tobias Burnus  <tobias@codesourcery.com>
+
+	PR fortran/58331
+	* interface.cc (compare_parameter): Adjust check of array dummy
+	arguments to handle the case of CLASS variables.
+
 2023-03-11  Harald Anlauf  <anlauf@gmx.de>
 
 	PR fortran/106945
diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index 36b07e9a458..218d6096a86 100644
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,9 @@
+2023-03-15  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	PR modula2/109125
+	* gm2-libs-ch/dtoa.cc (dtoa_strtod): Replace int with bool.
+	* gm2-libs-ch/ldtoa.cc (ldtoa_strtold): Replace int with bool.
+
 2023-03-14  Gaius Mulley  <gaiusmod2@gmail.com>
 
 	PR modula2/109125
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9b9d2e27765..a52a0e2312b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,131 @@
+2023-03-15  Jason Merrill  <jason@redhat.com>
+
+	PR c++/103871
+	PR c++/98056
+	* g++.dg/coroutines/co-await-initlist1.C: New test.
+
+2023-03-15  David Malcolm  <dmalcolm@redhat.com>
+
+	PR analyzer/109097
+	* c-c++-common/diagnostic-format-sarif-file-1.c: Verify that we
+	have an invocation object marked as succeeding, with no
+	notifications.
+	* gcc.dg/plugin/crash-test-ice-sarif.c: New test.
+	* gcc.dg/plugin/crash-test-ice-stderr.c: New test.
+	* gcc.dg/plugin/crash-test-write-though-null-sarif.c: New test.
+	* gcc.dg/plugin/crash-test-write-though-null-stderr.c: New test.
+	* gcc.dg/plugin/crash_test_plugin.c: New plugin.
+	* gcc.dg/plugin/plugin.exp (plugin_test_list): Add the new plugin
+	and test cases.
+
+2023-03-15  Uros Bizjak  <ubizjak@gmail.com>
+
+	* gcc.target/i386/merge-1.c (dg-options): Use -mno-sse4.
+	* gcc.target/i386/sse2-mmx-21.c (dg-options): Ditto.
+	* gcc.target/i386/sse-movss-4.c (dg-options):
+	Use -mno-sse4.  Simplify scan-assembler-not strings.
+	* gcc.target/i386/sse2-movsd-3.c (dg-options): Ditto.
+	* gcc.target/i386/sse2-mmx-movss-1.c: New test.
+
+2023-03-15  Harald Anlauf  <anlauf@gmx.de>
+	    Tobias Burnus  <tobias@codesourcery.com>
+
+	PR fortran/58331
+	* gfortran.dg/class_dummy_10.f90: New test.
+
+2023-03-15  Marek Polacek  <polacek@redhat.com>
+
+	PR c++/107280
+	* g++.dg/cpp1z/constexpr-lambda28.C: New test.
+
+2023-03-15  Richard Biener  <rguenther@suse.de>
+
+	* g++.dg/warn/Wuse-after-free3.C: Remove expected duplicate
+	diagnostic.
+
+2023-03-15  Jason Merrill  <jason@redhat.com>
+
+	PR c++/58538
+	* g++.dg/template/ttp7.C: Remove expected error.
+
+2023-03-15  Jason Merrill  <jason@redhat.com>
+
+	PR c++/108179
+	PR c++/104107
+	PR c++/95036
+	* g++.dg/template/ttp35.C: New test.
+
+2023-03-15  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/109139
+	* gcc.dg/torture/pr109139.c: New testcase.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* gcc.target/riscv/xtheadmempair-1.c: New test.
+	* gcc.target/riscv/xtheadmempair-2.c: New test.
+	* gcc.target/riscv/xtheadmempair-3.c: New test.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* gcc.target/riscv/xtheadfmv-fmv.c: New test.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* gcc.target/riscv/xtheadmac-mula-muls.c: New test.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c: New test.
+	* gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c: New test.
+	* gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c: New test.
+	* gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c: New test.
+	* gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c: New test.
+	* gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c: New test.
+	* gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c: New test.
+	* gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c: New test.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* gcc.target/riscv/xtheadbb-ext.c: New test.
+	* gcc.target/riscv/xtheadbb-extu-2.c: New test.
+	* gcc.target/riscv/xtheadbb-extu.c: New test.
+	* gcc.target/riscv/xtheadbb-ff1.c: New test.
+	* gcc.target/riscv/xtheadbb-rev.c: New test.
+	* gcc.target/riscv/xtheadbb-srri.c: New test.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* gcc.target/riscv/xtheadbs-tst.c: New test.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* gcc.target/riscv/xtheadba-addsl.c: New test.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* gcc.target/riscv/mcpu-thead-c906.c: New test.
+
+2023-03-15  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* gcc.target/riscv/xtheadba.c: New test.
+	* gcc.target/riscv/xtheadbb.c: New test.
+	* gcc.target/riscv/xtheadbs.c: New test.
+	* gcc.target/riscv/xtheadcmo.c: New test.
+	* gcc.target/riscv/xtheadcondmov.c: New test.
+	* gcc.target/riscv/xtheadfmemidx.c: New test.
+	* gcc.target/riscv/xtheadfmv.c: New test.
+	* gcc.target/riscv/xtheadint.c: New test.
+	* gcc.target/riscv/xtheadmac.c: New test.
+	* gcc.target/riscv/xtheadmemidx.c: New test.
+	* gcc.target/riscv/xtheadmempair.c: New test.
+	* gcc.target/riscv/xtheadsync.c: New test.
+
+2023-03-15  Hu, Lin1  <lin1.hu@intel.com>
+
+	PR target/109117
+	* gcc.target/i386/pr109117-1.c: New test.
+
 2023-03-15  Jonathan Yong  <10walls@gmail.com>
 
 	* gcc.dg/pic-2.c: Fix expected __PIC__ value.
diff --git a/libgm2/ChangeLog b/libgm2/ChangeLog
index 598b10f4bf3..0b9b6379dcb 100644
--- a/libgm2/ChangeLog
+++ b/libgm2/ChangeLog
@@ -1,3 +1,11 @@
+2023-03-15  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	PR modula2/109125
+	* libm2pim/dtoa.cc (TRUE): Remove.
+	(FALSE): Remove.  Replace int with bool.
+	* libm2pim/ldtoa.cc (TRUE): Remove.
+	(FALSE): Remove.  Replace int with bool.
+
 2023-03-14  Gaius Mulley  <gaiusmod2@gmail.com>
 
 	PR modula2/109125