[gcc r13-6829] amdgcn: Fix register size bug

[gcc r13-6829] amdgcn: Fix register size bug

[Andrew Stubbs]

https://gcc.gnu.org/g:3b97715af0e848ef8703ac04665bde562b2ac159

commit r13-6829-g3b97715af0e848ef8703ac04665bde562b2ac159
Author: Andrew Stubbs <ams@codesourcery.com>
Date:   Fri Mar 17 11:04:12 2023 +0000

    amdgcn: Fix register size bug
    
    Fix an issue in which "vectors" of duplicate entries placed in scalar
    registers caused the following 63 registers to be marked live, for the
    purpose of prologue generation, which resulted in stack corruption.
    
    gcc/ChangeLog:
    
            * config/gcn/gcn.cc (gcn_class_max_nregs): Handle vectors in SGPRs.
            (move_callee_saved_registers): Detect the bug condition early.

Diff:
---
 gcc/config/gcn/gcn.cc | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc
index 5bf88e98083..a7d278cd2f8 100644
--- a/gcc/config/gcn/gcn.cc
+++ b/gcc/config/gcn/gcn.cc
@@ -492,6 +492,15 @@ gcn_class_max_nregs (reg_class_t rclass, machine_mode mode)
     }
   else if (rclass == VCC_CONDITIONAL_REG && mode == BImode)
     return 2;
+
+  /* Vector modes in SGPRs are not supposed to happen (disallowed by
+     gcn_hard_regno_mode_ok), but there are some patterns that have an "Sv"
+     constraint and are used by splitters, post-reload.
+     This ensures that we don't accidentally mark the following 63 scalar
+     registers as "live".  */
+  if (rclass == SGPR_REGS && VECTOR_MODE_P (mode))
+    return CEIL (GET_MODE_SIZE (GET_MODE_INNER (mode)), 4);
+
   return CEIL (GET_MODE_SIZE (mode), 4);
 }
 
@@ -3239,6 +3248,10 @@ move_callee_saved_registers (rtx sp, machine_function *offsets,
       emit_insn (move_vectors);
       emit_insn (move_scalars);
     }
+
+  /* This happens when a new register becomes "live" after reload.
+     Check your splitters!  */
+  gcc_assert (offset <= offsets->callee_saves);
 }
 
 /* Generate prologue.  Called from gen_prologue during pro_and_epilogue pass.