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* [gcc(refs/users/meissner/heads/work117)] Revert patches
@ 2023-04-06 19:42 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-06 19:42 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3a9afb6ee83d11739052a515c8c5ec27eb9c411e
commit 3a9afb6ee83d11739052a515c8c5ec27eb9c411e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 6 15:42:30 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.md | 6 +---
gcc/config/rs6000/vsx.md | 6 ++--
gcc/testsuite/gcc.target/powerpc/pr70243-2.c | 41 ----------------------------
gcc/testsuite/gcc.target/powerpc/pr70243.c | 41 ----------------------------
4 files changed, 3 insertions(+), 91 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7fea6a40e0c..44f7dd509cb 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -354,7 +354,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,fastmath"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -402,10 +402,6 @@
(and (eq_attr "isa" "p10")
(match_test "TARGET_POWER10"))
(const_int 1)
-
- (and (eq_attr "isa" "fastmath")
- (match_test "flag_unsafe_math_optimizations"))
- (const_int 1)
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 85d4ac5082f..0865608f94a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2025,8 +2025,7 @@
xvmaddasp %x0,%x1,%x2
xvmaddmsp %x0,%x1,%x3
vmaddfp %0,%1,%2,%3"
- [(set_attr "type" "vecfloat")
- (set_attr "isa" "*,*,fastmath")])
+ [(set_attr "type" "vecfloat")])
(define_insn "*vsx_fmav2df4"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,wa")
@@ -2079,8 +2078,7 @@
xvnmsubasp %x0,%x1,%x2
xvnmsubmsp %x0,%x1,%x3
vnmsubfp %0,%1,%2,%3"
- [(set_attr "type" "vecfloat")
- (set_attr "isa" "*,*,fastmath")])
+ [(set_attr "type" "vecfloat")])
(define_insn "*vsx_nfmsv2df4"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243-2.c b/gcc/testsuite/gcc.target/powerpc/pr70243-2.c
deleted file mode 100644
index 2a4c2b17f6f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr70243-2.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-Ofast -mvsx" } */
-
-/* PR 70423, Make sure we don't generate fmaddfp or fnmsubfp unless -ffast-math
- is used. These instructions do not round the same way the normal VSX
- instructions do. These tests are written where the 3 inputs and target are
- all separate registers where the register allocator would prefer to issue
- the 4 argument FMA instruction over the 3 argument instruction plus an extra
- move. */
-
-#include <altivec.h>
-
-vector float
-do_add1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return (a * b) + c;
-}
-
-vector float
-do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return -((a * b) - c);
-}
-
-vector float
-do_add2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_madd (a, b, c);
-}
-
-vector float
-do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_nmsub (a, b, c);
-}
-
-/* { dg-final { scan-assembler-not "xvmaddsp" } } */
-/* { dg-final { scan-assembler-not "xvnmsubsp" } } */
-/* { dg-final { scan-assembler "fmaddfp" } } */
-/* { dg-final { scan-assembler "fnmsubfp" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243.c b/gcc/testsuite/gcc.target/powerpc/pr70243.c
deleted file mode 100644
index 7860767d83f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr70243.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* PR 70423, Make sure we don't generate fmaddfp or fnmsubfp unless -ffast-math
- is used. These instructions do not round the same way the normal VSX
- instructions do. These tests are written where the 3 inputs and target are
- all separate registers where the register allocator would prefer to issue
- the 4 argument FMA instruction over the 3 argument instruction plus an extra
- move. */
-
-#include <altivec.h>
-
-vector float
-do_add1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return (a * b) + c;
-}
-
-vector float
-do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return -((a * b) - c);
-}
-
-vector float
-do_add2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_madd (a, b, c);
-}
-
-vector float
-do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_nmsub (a, b, c);
-}
-
-/* { dg-final { scan-assembler "xvmaddsp" } } */
-/* { dg-final { scan-assembler "xvnmsubsp" } } */
-/* { dg-final { scan-assembler-not "fmaddfp" } } */
-/* { dg-final { scan-assembler-not "fnmsubfp" } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work117)] Revert patches
@ 2023-04-07 21:26 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-07 21:26 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1ceebb869a56a354e47268c2d7419a3ff583ffa2
commit 1ceebb869a56a354e47268c2d7419a3ff583ffa2
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 7 17:26:32 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 31 ++++++++++++----------
gcc/testsuite/gcc.target/powerpc/pr70243.c | 41 ------------------------------
2 files changed, 17 insertions(+), 55 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b7d7c313bdd..0865608f94a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2009,20 +2009,22 @@
"x<VSv>tsqrt<sd>p %0,%x1"
[(set_attr "type" "<VStype_simple>")])
-;; Fused vector multiply/add instructions. Do not use the classical Altivec
-;; versions of fma (vmaddfp and vnmsubfp). Those instructions allows the
-;; target to be a separate register from the 3 inputs, but they have different
-;; rounding behaviors.
+;; Fused vector multiply/add instructions. Support the classical Altivec
+;; versions of fma, which allows the target to be a separate register from the
+;; 3 inputs. Under VSX, the target must be either the addend or the first
+;; multiply.
+
(define_insn "*vsx_fmav4sf4"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
(fma:V4SF
- (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa")
- (match_operand:V4SF 2 "vsx_register_operand" "wa,0")
- (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))]
+ (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
+ (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
+ (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"@
xvmaddasp %x0,%x1,%x2
- xvmaddmsp %x0,%x1,%x3"
+ xvmaddmsp %x0,%x1,%x3
+ vmaddfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
(define_insn "*vsx_fmav2df4"
@@ -2064,17 +2066,18 @@
[(set_attr "type" "<VStype_mul>")])
(define_insn "*vsx_nfmsv4sf4"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
(neg:V4SF
(fma:V4SF
- (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa")
- (match_operand:V4SF 2 "vsx_register_operand" "wa,0")
+ (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
+ (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
(neg:V4SF
- (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))))]
+ (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"@
xvnmsubasp %x0,%x1,%x2
- xvnmsubmsp %x0,%x1,%x3"
+ xvnmsubmsp %x0,%x1,%x3
+ vnmsubfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
(define_insn "*vsx_nfmsv2df4"
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243.c b/gcc/testsuite/gcc.target/powerpc/pr70243.c
deleted file mode 100644
index 1dfc13a8864..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr70243.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* PR 70423, Make sure we don't generate fmaddfp or fnmsubfp. These
- instructions have different rounding modes than the VSX instructions
- xvmaddsp and xvnmsubsp. These tests are written where the 3 inputs and
- target are all separate registers. Because fmaddfp and fnmsubfp are no
- longer generated the compiler will have to generate an xsmaddsp or xsnmsubsp
- instruction followed by a move operation. */
-
-#include <altivec.h>
-
-vector float
-do_add1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return (a * b) + c;
-}
-
-vector float
-do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return -((a * b) - c);
-}
-
-vector float
-do_add2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_madd (a, b, c);
-}
-
-vector float
-do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_nmsub (a, b, c);
-}
-
-/* { dg-final { scan-assembler "xvmaddsp" } } */
-/* { dg-final { scan-assembler "xvnmsubsp" } } */
-/* { dg-final { scan-assembler-not "fmaddfp" } } */
-/* { dg-final { scan-assembler-not "fnmsubfp" } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work117)] Revert patches
@ 2023-04-07 18:27 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-07 18:27 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f0f18f83db79c42008c448f376e59b930acd1b53
commit f0f18f83db79c42008c448f376e59b930acd1b53
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 7 14:27:23 2023 -0400
Revert patches
Diff:
---
gcc/ChangeLog.meissner | 66 +---------------------------
gcc/config/rs6000/rs6000.md | 6 +--
gcc/config/rs6000/vsx.md | 17 +++----
gcc/testsuite/gcc.target/powerpc/pr70243-2.c | 41 -----------------
gcc/testsuite/gcc.target/powerpc/pr70243.c | 41 -----------------
5 files changed, 9 insertions(+), 162 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 801fea03f4b..80190b5d6b4 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,68 +1,4 @@
-==================== Branch work117, patch #3 ====================
-
-PR target/70243: Do not generate vmaddfp and vnmsubfp
-
-This is version 2 of the patch. The first version was posted on April 6th.
-
-In this version, I eliminated the changes to Altivec.md that added checks to
-altivec_fmav4sf4 and altivec_vnmsubfp. After writing the code, I remembered
-that VECTOR_UNIT_ALTIVEC_P that is used by those insns will not be true if the
-VSX instruction set is enabled, so no additional test is needed.
-
-As we discussed in a private chat room, I modified the code to generate vmaddfp
-and vnmsubfp if -Ofast (-ffast-math) is used. This allows the compiler to
-eliminate the extra move if the user does not care about strict floating point
-code generation, but it generates only the VSX instructions in the normal
-case.
-
-I reworked the examples and split them into two tests to test both the normal
-case when -Ofast is not used and when it is used.
-
-I also fixed the instructions mentioned in the comments to be the actual
-instructions (vmaddfp and vnmsubfp) instead of fmaddfp and fnmsubdp. Sorry
-about tat.
-
-The AltiVec (VMX) instructions vmaddfp and vnmsubfp have different rounding
-behaviors than the VSX xvmadd{a,m}sp and xvnmsub{a,m}sp instructions. In
-particular, generating these instructions seems to break Eigen.
-
-The bug is that GCC has generated the VMX vmaddfp and vnmsubfp instructions on
-VSX systems as an alternative to the xsmadd{a,m}sp and xsnmsub{a,m}sp
-instructions. The advantage of the VMX instructions is that they are 4 operand
-instructions (i.e. the target register does not have to overlap with one of the
-input registers). This can mean that the compiler can eliminate an extra move
-instruction. The disadvantage of generating these instructions is it does not
-round the same was as the VSX instructions.
-
-This patch will only generate the VMX vmaddfp and vnmsubfp instructions as
-alternatives in the VSX instruction insn support if -Ofast (-ffast-math) is
-used. I also added 2 tests to the regression suite.
-
-I have done bootstrap builds on power9 little endian (with both IEEE long
-double and IBM long double). I have also done the builds and test on a power8
-big endian system (testing both 32-bit and 64-bit code generation). Chip has
-verified that it fixes the problem that Eigen encountered. Can I check this
-into the master GCC branch? After a burn-in period, can I check this patch
-into the active GCC branches?
-
-Thanks in advance.
-
-2023-04-07 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/
-
- PR target/70243
- * config/rs6000/rs6000.md (isa attribute): Add fastmath.
- (enabled attribute): Add support for fastmath.
- * config/rs6000/vsx.md (vsx_fmav4sf4): Set the isa attribute to
- fastmath to disable Altivec instruction generatins normally.
- (vsx_nfmsv4sf4): Likewise.
-
-gcc/testsuite/
-
- PR target/70243
- * gcc.target/powerpc/pr70243.c: New test.
- * gcc.target/powerpc/pr70243-2.c: New test.
+==================== Branch work117, patch #3 was reverted ====================
==================== Branch work117, patch #2 was reverted ====================
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7fea6a40e0c..44f7dd509cb 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -354,7 +354,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,fastmath"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -402,10 +402,6 @@
(and (eq_attr "isa" "p10")
(match_test "TARGET_POWER10"))
(const_int 1)
-
- (and (eq_attr "isa" "fastmath")
- (match_test "flag_unsafe_math_optimizations"))
- (const_int 1)
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 7f64a2dd356..0865608f94a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2009,12 +2009,11 @@
"x<VSv>tsqrt<sd>p %0,%x1"
[(set_attr "type" "<VStype_simple>")])
-;; Fused vector multiply/add instructions. Under VSX, the target must be either
-;; the addend or the first multiply. If the user used -Ofast, also support the
-;; classical VMX versions of fma (vmaddfp and vnmsubfp), which allows the
-;; target to be a separate register from the 3 inputs. This restriction is due
-;; to the fact that vmaddfp and vnmsubfp have different rounding behaviors
-;; compared to xvmadd{a,m}sp or xvnmsub{a,m}sp.
+;; Fused vector multiply/add instructions. Support the classical Altivec
+;; versions of fma, which allows the target to be a separate register from the
+;; 3 inputs. Under VSX, the target must be either the addend or the first
+;; multiply.
+
(define_insn "*vsx_fmav4sf4"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
(fma:V4SF
@@ -2026,8 +2025,7 @@
xvmaddasp %x0,%x1,%x2
xvmaddmsp %x0,%x1,%x3
vmaddfp %0,%1,%2,%3"
- [(set_attr "type" "vecfloat")
- (set_attr "isa" "*,*,fastmath")])
+ [(set_attr "type" "vecfloat")])
(define_insn "*vsx_fmav2df4"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,wa")
@@ -2080,8 +2078,7 @@
xvnmsubasp %x0,%x1,%x2
xvnmsubmsp %x0,%x1,%x3
vnmsubfp %0,%1,%2,%3"
- [(set_attr "type" "vecfloat")
- (set_attr "isa" "*,*,fastmath")])
+ [(set_attr "type" "vecfloat")])
(define_insn "*vsx_nfmsv2df4"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243-2.c b/gcc/testsuite/gcc.target/powerpc/pr70243-2.c
deleted file mode 100644
index ef475f39b12..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr70243-2.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-Ofast -mvsx" } */
-
-/* PR 70423. Make sure we don't generate vmaddfp or vnmsubfp unless -Ofast is
- used. These instructions do not round the same way the normal VSX
- instructions do. These tests are written where the 3 inputs and target are
- all separate registers where the register allocator would prefer to issue
- the 4 argument FMA instruction over the 3 argument instruction plus an extra
- move. */
-
-#include <altivec.h>
-
-vector float
-do_add1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return (a * b) + c;
-}
-
-vector float
-do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return -((a * b) - c);
-}
-
-vector float
-do_add2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_madd (a, b, c);
-}
-
-vector float
-do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_nmsub (a, b, c);
-}
-
-/* { dg-final { scan-assembler-not {\mxvmadd[am]sp\M} } } */
-/* { dg-final { scan-assembler-not {\mxvnmsub[am]sp\M} } } */
-/* { dg-final { scan-assembler {\mvmaddfp\M} } } */
-/* { dg-final { scan-assembler {\mvnmsubfp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243.c b/gcc/testsuite/gcc.target/powerpc/pr70243.c
deleted file mode 100644
index c1a5c676fc3..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr70243.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* PR 70423. Make sure we don't generate vmaddfp or vnmsubfp unless -Ofast is
- used. These instructions do not round the same way the normal VSX
- instructions do. These tests are written where the 3 inputs and target are
- all separate registers where the register allocator would prefer to issue
- the 4 argument FMA instruction over the 3 argument instruction plus an extra
- move. */
-
-#include <altivec.h>
-
-vector float
-do_add1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return (a * b) + c;
-}
-
-vector float
-do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return -((a * b) - c);
-}
-
-vector float
-do_add2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_madd (a, b, c);
-}
-
-vector float
-do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_nmsub (a, b, c);
-}
-
-/* { dg-final { scan-assembler {\mxvmadd[am]sp\M} } } */
-/* { dg-final { scan-assembler {\mxvnmsub[am]sp\M} } } */
-/* { dg-final { scan-assembler-not {\mvmaddfp\M} } } */
-/* { dg-final { scan-assembler-not {\mvnmsubfp\M} } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work117)] Revert patches
@ 2023-04-07 3:37 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-07 3:37 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:c2aeaf548856dc80a4f654cc945d5b2881629e33
commit c2aeaf548856dc80a4f654cc945d5b2881629e33
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 6 23:37:20 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.md | 6 +---
gcc/config/rs6000/vsx.md | 6 ++--
gcc/testsuite/gcc.target/powerpc/pr70243-2.c | 41 ----------------------------
gcc/testsuite/gcc.target/powerpc/pr70243.c | 41 ----------------------------
4 files changed, 3 insertions(+), 91 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7fea6a40e0c..44f7dd509cb 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -354,7 +354,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,fastmath"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -402,10 +402,6 @@
(and (eq_attr "isa" "p10")
(match_test "TARGET_POWER10"))
(const_int 1)
-
- (and (eq_attr "isa" "fastmath")
- (match_test "flag_unsafe_math_optimizations"))
- (const_int 1)
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 85d4ac5082f..0865608f94a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2025,8 +2025,7 @@
xvmaddasp %x0,%x1,%x2
xvmaddmsp %x0,%x1,%x3
vmaddfp %0,%1,%2,%3"
- [(set_attr "type" "vecfloat")
- (set_attr "isa" "*,*,fastmath")])
+ [(set_attr "type" "vecfloat")])
(define_insn "*vsx_fmav2df4"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,wa")
@@ -2079,8 +2078,7 @@
xvnmsubasp %x0,%x1,%x2
xvnmsubmsp %x0,%x1,%x3
vnmsubfp %0,%1,%2,%3"
- [(set_attr "type" "vecfloat")
- (set_attr "isa" "*,*,fastmath")])
+ [(set_attr "type" "vecfloat")])
(define_insn "*vsx_nfmsv2df4"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243-2.c b/gcc/testsuite/gcc.target/powerpc/pr70243-2.c
deleted file mode 100644
index 6eb3a53a76e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr70243-2.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-Ofast -mvsx" } */
-
-/* PR 70423, Make sure we don't generate fmaddfp or fnmsubfp unless -ffast-math
- is used. These instructions do not round the same way the normal VSX
- instructions do. These tests are written where the 3 inputs and target are
- all separate registers where the register allocator would prefer to issue
- the 4 argument FMA instruction over the 3 argument instruction plus an extra
- move. */
-
-#include <altivec.h>
-
-vector float
-do_add1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return (a * b) + c;
-}
-
-vector float
-do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return -((a * b) - c);
-}
-
-vector float
-do_add2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_madd (a, b, c);
-}
-
-vector float
-do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_nmsub (a, b, c);
-}
-
-/* { dg-final { scan-assembler-not {\mxvmadd[am]sp\M} } } */
-/* { dg-final { scan-assembler-not {\mxvnmsub[am]sp\M} } } */
-/* { dg-final { scan-assembler {\mvmaddfp\M} } } */
-/* { dg-final { scan-assembler {\mvnmsubfp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243.c b/gcc/testsuite/gcc.target/powerpc/pr70243.c
deleted file mode 100644
index 3d8ca9cff29..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr70243.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* PR 70423, Make sure we don't generate fmaddfp or fnmsubfp unless -ffast-math
- is used. These instructions do not round the same way the normal VSX
- instructions do. These tests are written where the 3 inputs and target are
- all separate registers where the register allocator would prefer to issue
- the 4 argument FMA instruction over the 3 argument instruction plus an extra
- move. */
-
-#include <altivec.h>
-
-vector float
-do_add1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return (a * b) + c;
-}
-
-vector float
-do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return -((a * b) - c);
-}
-
-vector float
-do_add2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_madd (a, b, c);
-}
-
-vector float
-do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_nmsub (a, b, c);
-}
-
-/* { dg-final { scan-assembler {\mxvmadd[am]sp\M} } } */
-/* { dg-final { scan-assembler {\mxvnmsub[am]sp\M} } } */
-/* { dg-final { scan-assembler-not {\mvmaddfp\M} } } */
-/* { dg-final { scan-assembler-not {\mvnmsubfp\M} } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work117)] Revert patches
@ 2023-04-06 20:28 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-06 20:28 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0fbec939e9eea2e4987badd3eed13d9b35fd68c2
commit 0fbec939e9eea2e4987badd3eed13d9b35fd68c2
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 6 16:28:43 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.md | 6 +---
gcc/config/rs6000/vsx.md | 6 ++--
gcc/testsuite/gcc.target/powerpc/pr70243-2.c | 41 ----------------------------
gcc/testsuite/gcc.target/powerpc/pr70243.c | 41 ----------------------------
4 files changed, 3 insertions(+), 91 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7fea6a40e0c..44f7dd509cb 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -354,7 +354,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,fastmath"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -402,10 +402,6 @@
(and (eq_attr "isa" "p10")
(match_test "TARGET_POWER10"))
(const_int 1)
-
- (and (eq_attr "isa" "fastmath")
- (match_test "flag_unsafe_math_optimizations"))
- (const_int 1)
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 85d4ac5082f..0865608f94a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2025,8 +2025,7 @@
xvmaddasp %x0,%x1,%x2
xvmaddmsp %x0,%x1,%x3
vmaddfp %0,%1,%2,%3"
- [(set_attr "type" "vecfloat")
- (set_attr "isa" "*,*,fastmath")])
+ [(set_attr "type" "vecfloat")])
(define_insn "*vsx_fmav2df4"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,wa")
@@ -2079,8 +2078,7 @@
xvnmsubasp %x0,%x1,%x2
xvnmsubmsp %x0,%x1,%x3
vnmsubfp %0,%1,%2,%3"
- [(set_attr "type" "vecfloat")
- (set_attr "isa" "*,*,fastmath")])
+ [(set_attr "type" "vecfloat")])
(define_insn "*vsx_nfmsv2df4"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243-2.c b/gcc/testsuite/gcc.target/powerpc/pr70243-2.c
deleted file mode 100644
index 27460150631..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr70243-2.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-Ofast -mvsx" } */
-
-/* PR 70423, Make sure we don't generate fmaddfp or fnmsubfp unless -ffast-math
- is used. These instructions do not round the same way the normal VSX
- instructions do. These tests are written where the 3 inputs and target are
- all separate registers where the register allocator would prefer to issue
- the 4 argument FMA instruction over the 3 argument instruction plus an extra
- move. */
-
-#include <altivec.h>
-
-vector float
-do_add1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return (a * b) + c;
-}
-
-vector float
-do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return -((a * b) - c);
-}
-
-vector float
-do_add2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_madd (a, b, c);
-}
-
-vector float
-do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_nmsub (a, b, c);
-}
-
-/* { dg-final { scan-assembler-not {\mxvmadd[am]sp\M} } } */
-/* { dg-final { scan-assembler-not {\mxvnmsub[am]sp\M} } } */
-/* { dg-final { scan-assembler {\mfmaddfp\M} } } */
-/* { dg-final { scan-assembler {\mfnmsubfp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243.c b/gcc/testsuite/gcc.target/powerpc/pr70243.c
deleted file mode 100644
index 91b75b68986..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr70243.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* PR 70423, Make sure we don't generate fmaddfp or fnmsubfp unless -ffast-math
- is used. These instructions do not round the same way the normal VSX
- instructions do. These tests are written where the 3 inputs and target are
- all separate registers where the register allocator would prefer to issue
- the 4 argument FMA instruction over the 3 argument instruction plus an extra
- move. */
-
-#include <altivec.h>
-
-vector float
-do_add1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return (a * b) + c;
-}
-
-vector float
-do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return -((a * b) - c);
-}
-
-vector float
-do_add2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_madd (a, b, c);
-}
-
-vector float
-do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_nmsub (a, b, c);
-}
-
-/* { dg-final { scan-assembler {\mxvmadd[am]sp\M} } } */
-/* { dg-final { scan-assembler {\mxvnmsub[am]sp\M} } } */
-/* { dg-final { scan-assembler-not {\mfmaddfp\M} } } */
-/* { dg-final { scan-assembler-not {\mfnmsubfp\M} } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work117)] Revert patches
@ 2023-04-06 18:45 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-06 18:45 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:84c9afc5445e46024ec42ce28a3d48495f29bb76
commit 84c9afc5445e46024ec42ce28a3d48495f29bb76
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 6 14:45:29 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.md | 6 +---
gcc/config/rs6000/vsx.md | 6 ++--
gcc/testsuite/gcc.target/powerpc/pr70243-2.c | 41 ----------------------------
gcc/testsuite/gcc.target/powerpc/pr70243.c | 41 ----------------------------
4 files changed, 3 insertions(+), 91 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 21eae610efc..44f7dd509cb 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -354,7 +354,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,fastmath"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -402,10 +402,6 @@
(and (eq_attr "isa" "p10")
(match_test "TARGET_POWER10"))
(const_int 1)
-
- (and (eq_attr "isa" "fastmath")
- (match_test "flag_unsafe_math_optimizations || flag_rounding_math"))
- (const_int 1)
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 85d4ac5082f..0865608f94a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2025,8 +2025,7 @@
xvmaddasp %x0,%x1,%x2
xvmaddmsp %x0,%x1,%x3
vmaddfp %0,%1,%2,%3"
- [(set_attr "type" "vecfloat")
- (set_attr "isa" "*,*,fastmath")])
+ [(set_attr "type" "vecfloat")])
(define_insn "*vsx_fmav2df4"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,wa")
@@ -2079,8 +2078,7 @@
xvnmsubasp %x0,%x1,%x2
xvnmsubmsp %x0,%x1,%x3
vnmsubfp %0,%1,%2,%3"
- [(set_attr "type" "vecfloat")
- (set_attr "isa" "*,*,fastmath")])
+ [(set_attr "type" "vecfloat")])
(define_insn "*vsx_nfmsv2df4"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243-2.c b/gcc/testsuite/gcc.target/powerpc/pr70243-2.c
deleted file mode 100644
index 5045e1271a2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr70243-2.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx -ffast-math" } */
-
-/* PR 70423, Make sure we don't generate fmaddfp or fnmsubfp unless -ffast-math
- is used. These instructions do not round the same way the normal VSX
- instructions do. These tests are written where the 3 inputs and target are
- all separate registers where the register allocator would prefer to issue
- the 4 argument FMA instruction over the 3 argument instruction plus an extra
- move. */
-
-#include <altivec.h>
-
-vector float
-do_add1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return (a * b) + c;
-}
-
-vector float
-do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return -((a * b) - c);
-}
-
-vector float
-do_add2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_madd (a, b, c);
-}
-
-vector float
-do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_nmsub (a, b, c);
-}
-
-/* { dg-final { scan-assembler-not "xvmaddsp" } } */
-/* { dg-final { scan-assembler-not "xvnmsubsp" } } */
-/* { dg-final { scan-assembler "fmaddfp" } } */
-/* { dg-final { scan-assembler "fnmsubfp" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243.c b/gcc/testsuite/gcc.target/powerpc/pr70243.c
deleted file mode 100644
index 7860767d83f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr70243.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* PR 70423, Make sure we don't generate fmaddfp or fnmsubfp unless -ffast-math
- is used. These instructions do not round the same way the normal VSX
- instructions do. These tests are written where the 3 inputs and target are
- all separate registers where the register allocator would prefer to issue
- the 4 argument FMA instruction over the 3 argument instruction plus an extra
- move. */
-
-#include <altivec.h>
-
-vector float
-do_add1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return (a * b) + c;
-}
-
-vector float
-do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return -((a * b) - c);
-}
-
-vector float
-do_add2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_madd (a, b, c);
-}
-
-vector float
-do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_nmsub (a, b, c);
-}
-
-/* { dg-final { scan-assembler "xvmaddsp" } } */
-/* { dg-final { scan-assembler "xvnmsubsp" } } */
-/* { dg-final { scan-assembler-not "fmaddfp" } } */
-/* { dg-final { scan-assembler-not "fnmsubfp" } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work117)] Revert patches
@ 2023-04-06 16:20 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-06 16:20 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9e2863188b453b5ed4df1f9ba9e4327aed8e513f
commit 9e2863188b453b5ed4df1f9ba9e4327aed8e513f
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 6 12:20:33 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/altivec.md | 9 ++-----
gcc/config/rs6000/vsx.md | 29 +++++++++++----------
gcc/testsuite/gcc.target/powerpc/pr70243.c | 41 ------------------------------
3 files changed, 18 insertions(+), 61 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 63eab228d0d..49b0c964f4d 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -750,15 +750,12 @@
;; Fused multiply add.
-;; If we are using VSX instructions, do not generate the vmaddfp instruction
-;; since is has different rounding behavior than the xvmaddsp instruction.
-
(define_insn "*altivec_fmav4sf4"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(fma:V4SF (match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")
(match_operand:V4SF 3 "register_operand" "v")))]
- "VECTOR_UNIT_ALTIVEC_P (V4SFmode) && !TARGET_VSX"
+ "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
"vmaddfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
@@ -987,8 +984,6 @@
[(set_attr "type" "vecsimple")])
;; Fused multiply subtract
-;; If we are using VSX instructions, do not generate the vnmsubfp instruction
-;; since is has different rounding behavior than the xvnmsubsp instruction.
(define_insn "*altivec_vnmsubfp"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(neg:V4SF
@@ -996,7 +991,7 @@
(match_operand:V4SF 2 "register_operand" "v")
(neg:V4SF
(match_operand:V4SF 3 "register_operand" "v")))))]
- "VECTOR_UNIT_ALTIVEC_P (V4SFmode) && !TARGET_VSX"
+ "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
"vnmsubfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 03c1d787b6c..0865608f94a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2009,20 +2009,22 @@
"x<VSv>tsqrt<sd>p %0,%x1"
[(set_attr "type" "<VStype_simple>")])
-;; Fused vector multiply/add instructions. Do not use the classical Altivec
-;; versions of fma. Those instructions allows the target to be a separate
-;; register from the 3 inputs, but they have different rounding behaviors.
+;; Fused vector multiply/add instructions. Support the classical Altivec
+;; versions of fma, which allows the target to be a separate register from the
+;; 3 inputs. Under VSX, the target must be either the addend or the first
+;; multiply.
(define_insn "*vsx_fmav4sf4"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
(fma:V4SF
- (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa")
- (match_operand:V4SF 2 "vsx_register_operand" "wa,0")
- (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))]
+ (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
+ (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
+ (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"@
xvmaddasp %x0,%x1,%x2
- xvmaddmsp %x0,%x1,%x3"
+ xvmaddmsp %x0,%x1,%x3
+ vmaddfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
(define_insn "*vsx_fmav2df4"
@@ -2064,17 +2066,18 @@
[(set_attr "type" "<VStype_mul>")])
(define_insn "*vsx_nfmsv4sf4"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
(neg:V4SF
(fma:V4SF
- (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa")
- (match_operand:V4SF 2 "vsx_register_operand" "wa,0")
+ (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
+ (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
(neg:V4SF
- (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))))]
+ (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"@
xvnmsubasp %x0,%x1,%x2
- xvnmsubmsp %x0,%x1,%x3"
+ xvnmsubmsp %x0,%x1,%x3
+ vnmsubfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
(define_insn "*vsx_nfmsv2df4"
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243.c b/gcc/testsuite/gcc.target/powerpc/pr70243.c
deleted file mode 100644
index 4ec54734f3e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr70243.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* PR 70423, Make sure we don't generate fmaddfp or fnmsubfp. These
- instructions have different rounding modes than the VSX instructions
- xvmaddsp and xvnmsubsp. These tests are written where the 3 inputs and
- target are all separate registers. Because fmaddfp and fnmsubfp are no
- longer generated the compiler will have to generate an xsmadd[am]sp or
- xsnmsub[am]sp instruction along with a move operation. */
-
-#include <altivec.h>
-
-vector float
-do_add1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return (a * b) + c;
-}
-
-vector float
-do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return -((a * b) - c);
-}
-
-vector float
-do_add2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_madd (a, b, c);
-}
-
-vector float
-do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_nmsub (a, b, c);
-}
-
-/* { dg-final { scan-assembler {\mxvmadd[am]sp\M} } } */
-/* { dg-final { scan-assembler {\mxvnmsub[am]sp\M} } } */
-/* { dg-final { scan-assembler-not {\mfmaddfp\M} } } */
-/* { dg-final { scan-assembler-not {\mfnmsubfp\M} } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work117)] Revert patches
@ 2023-04-06 3:10 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-06 3:10 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a92e6b0c7ff0ce7e04770792204fe4af54b7c45a
commit a92e6b0c7ff0ce7e04770792204fe4af54b7c45a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 5 23:10:56 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/altivec.md | 9 ++-----
gcc/config/rs6000/vsx.md | 29 +++++++++++----------
gcc/testsuite/gcc.target/powerpc/pr70243.c | 41 ------------------------------
3 files changed, 18 insertions(+), 61 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 63eab228d0d..49b0c964f4d 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -750,15 +750,12 @@
;; Fused multiply add.
-;; If we are using VSX instructions, do not generate the vmaddfp instruction
-;; since is has different rounding behavior than the xvmaddsp instruction.
-
(define_insn "*altivec_fmav4sf4"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(fma:V4SF (match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")
(match_operand:V4SF 3 "register_operand" "v")))]
- "VECTOR_UNIT_ALTIVEC_P (V4SFmode) && !TARGET_VSX"
+ "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
"vmaddfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
@@ -987,8 +984,6 @@
[(set_attr "type" "vecsimple")])
;; Fused multiply subtract
-;; If we are using VSX instructions, do not generate the vnmsubfp instruction
-;; since is has different rounding behavior than the xvnmsubsp instruction.
(define_insn "*altivec_vnmsubfp"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(neg:V4SF
@@ -996,7 +991,7 @@
(match_operand:V4SF 2 "register_operand" "v")
(neg:V4SF
(match_operand:V4SF 3 "register_operand" "v")))))]
- "VECTOR_UNIT_ALTIVEC_P (V4SFmode) && !TARGET_VSX"
+ "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
"vnmsubfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 03c1d787b6c..0865608f94a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2009,20 +2009,22 @@
"x<VSv>tsqrt<sd>p %0,%x1"
[(set_attr "type" "<VStype_simple>")])
-;; Fused vector multiply/add instructions. Do not use the classical Altivec
-;; versions of fma. Those instructions allows the target to be a separate
-;; register from the 3 inputs, but they have different rounding behaviors.
+;; Fused vector multiply/add instructions. Support the classical Altivec
+;; versions of fma, which allows the target to be a separate register from the
+;; 3 inputs. Under VSX, the target must be either the addend or the first
+;; multiply.
(define_insn "*vsx_fmav4sf4"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
(fma:V4SF
- (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa")
- (match_operand:V4SF 2 "vsx_register_operand" "wa,0")
- (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))]
+ (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
+ (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
+ (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"@
xvmaddasp %x0,%x1,%x2
- xvmaddmsp %x0,%x1,%x3"
+ xvmaddmsp %x0,%x1,%x3
+ vmaddfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
(define_insn "*vsx_fmav2df4"
@@ -2064,17 +2066,18 @@
[(set_attr "type" "<VStype_mul>")])
(define_insn "*vsx_nfmsv4sf4"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
(neg:V4SF
(fma:V4SF
- (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa")
- (match_operand:V4SF 2 "vsx_register_operand" "wa,0")
+ (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
+ (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
(neg:V4SF
- (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))))]
+ (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"@
xvnmsubasp %x0,%x1,%x2
- xvnmsubmsp %x0,%x1,%x3"
+ xvnmsubmsp %x0,%x1,%x3
+ vnmsubfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
(define_insn "*vsx_nfmsv2df4"
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243.c b/gcc/testsuite/gcc.target/powerpc/pr70243.c
deleted file mode 100644
index 1dfc13a8864..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr70243.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* PR 70423, Make sure we don't generate fmaddfp or fnmsubfp. These
- instructions have different rounding modes than the VSX instructions
- xvmaddsp and xvnmsubsp. These tests are written where the 3 inputs and
- target are all separate registers. Because fmaddfp and fnmsubfp are no
- longer generated the compiler will have to generate an xsmaddsp or xsnmsubsp
- instruction followed by a move operation. */
-
-#include <altivec.h>
-
-vector float
-do_add1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return (a * b) + c;
-}
-
-vector float
-do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return -((a * b) - c);
-}
-
-vector float
-do_add2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_madd (a, b, c);
-}
-
-vector float
-do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_nmsub (a, b, c);
-}
-
-/* { dg-final { scan-assembler "xvmaddsp" } } */
-/* { dg-final { scan-assembler "xvnmsubsp" } } */
-/* { dg-final { scan-assembler-not "fmaddfp" } } */
-/* { dg-final { scan-assembler-not "fnmsubfp" } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work117)] Revert patches
@ 2023-04-06 2:42 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-06 2:42 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:927a6371823e2be3b383415a0f072ab8a04467f5
commit 927a6371823e2be3b383415a0f072ab8a04467f5
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 5 22:42:40 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/altivec.md | 9 ++-----
gcc/config/rs6000/vsx.md | 29 ++++++++++++----------
gcc/testsuite/gcc.target/powerpc/pr70243.c | 39 ------------------------------
3 files changed, 18 insertions(+), 59 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 63eab228d0d..49b0c964f4d 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -750,15 +750,12 @@
;; Fused multiply add.
-;; If we are using VSX instructions, do not generate the vmaddfp instruction
-;; since is has different rounding behavior than the xvmaddsp instruction.
-
(define_insn "*altivec_fmav4sf4"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(fma:V4SF (match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")
(match_operand:V4SF 3 "register_operand" "v")))]
- "VECTOR_UNIT_ALTIVEC_P (V4SFmode) && !TARGET_VSX"
+ "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
"vmaddfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
@@ -987,8 +984,6 @@
[(set_attr "type" "vecsimple")])
;; Fused multiply subtract
-;; If we are using VSX instructions, do not generate the vnmsubfp instruction
-;; since is has different rounding behavior than the xvnmsubsp instruction.
(define_insn "*altivec_vnmsubfp"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(neg:V4SF
@@ -996,7 +991,7 @@
(match_operand:V4SF 2 "register_operand" "v")
(neg:V4SF
(match_operand:V4SF 3 "register_operand" "v")))))]
- "VECTOR_UNIT_ALTIVEC_P (V4SFmode) && !TARGET_VSX"
+ "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
"vnmsubfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 03c1d787b6c..0865608f94a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2009,20 +2009,22 @@
"x<VSv>tsqrt<sd>p %0,%x1"
[(set_attr "type" "<VStype_simple>")])
-;; Fused vector multiply/add instructions. Do not use the classical Altivec
-;; versions of fma. Those instructions allows the target to be a separate
-;; register from the 3 inputs, but they have different rounding behaviors.
+;; Fused vector multiply/add instructions. Support the classical Altivec
+;; versions of fma, which allows the target to be a separate register from the
+;; 3 inputs. Under VSX, the target must be either the addend or the first
+;; multiply.
(define_insn "*vsx_fmav4sf4"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
(fma:V4SF
- (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa")
- (match_operand:V4SF 2 "vsx_register_operand" "wa,0")
- (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))]
+ (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
+ (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
+ (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"@
xvmaddasp %x0,%x1,%x2
- xvmaddmsp %x0,%x1,%x3"
+ xvmaddmsp %x0,%x1,%x3
+ vmaddfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
(define_insn "*vsx_fmav2df4"
@@ -2064,17 +2066,18 @@
[(set_attr "type" "<VStype_mul>")])
(define_insn "*vsx_nfmsv4sf4"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
(neg:V4SF
(fma:V4SF
- (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa")
- (match_operand:V4SF 2 "vsx_register_operand" "wa,0")
+ (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
+ (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
(neg:V4SF
- (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))))]
+ (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"@
xvnmsubasp %x0,%x1,%x2
- xvnmsubmsp %x0,%x1,%x3"
+ xvnmsubmsp %x0,%x1,%x3
+ vnmsubfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
(define_insn "*vsx_nfmsv2df4"
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243.c b/gcc/testsuite/gcc.target/powerpc/pr70243.c
deleted file mode 100644
index 5dc4e997193..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr70243.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* { dg-do compile { } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power7" } */
-
-/* PR 70423, Make sure we don't generate fmaddfp or fnmsubfp. These
- instructions have different rounding modes than the VSX instructions
- xvmaddsp and xvnmsubsp. */
-
-#include <altivec.h>
-
-vector float
-do_add1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return (a * b) + c;
-}
-
-vector float
-do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return -((a * b) - c);
-}
-
-vector float
-do_add2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_madd (a, b, c);
-}
-
-vector float
-do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
-{
- return vec_nmsub (a, b, c);
-}
-
-/* { dg-final { scan-assembler "xvmaddsp" } } */
-/* { dg-final { scan-assembler "xvnmsubsp" } } */
-/* { dg-final { scan-assembler-not "fmaddfp" } } */
-/* { dg-final { scan-assembler-not "fnmsubfp" } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
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