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* [gcc(refs/users/meissner/heads/work118)] Revert patches
@ 2023-04-13 18:43 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2023-04-13 18:43 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3a3530597ca039183567526f066f6180337cb7a5
commit 3a3530597ca039183567526f066f6180337cb7a5
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 13 14:43:41 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 98 +++++-------------------------------------------
1 file changed, 10 insertions(+), 88 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index fc7dd63ff3f..d615474df01 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,8 +3549,7 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory with constant element number
-(define_insn_and_split "*vsx_extract_v4sf_load"
+(define_insn_and_split "*vsx_extract_v4sf_<mode>_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
(match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
@@ -3558,12 +3557,9 @@
(clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
-
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
@@ -3571,30 +3567,6 @@
(set_attr "length" "8")
(set_attr "isa" "*,p7v,p9v,*")])
-;; V4SF extract from memory and convert to DFmode with constant element number
-(define_insn_and_split "*vsx_extract_v4sf_to_df_load"
- [(set (match_operand:DF 0 "register_operand" "=f,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
-
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p8v")])
-
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
@@ -3613,7 +3585,7 @@
DONE;
})
-;; V4SF extract from memory with variable element number
+;; Variable V4SF extract from memory
(define_insn_and_split "*vsx_extract_v4sf_var_load"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
@@ -3622,39 +3594,14 @@
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
-
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory and convert to DFmode with variable element number
-(define_insn_and_split "*vsx_extract_v4sf_to_df_var_load"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
-
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
@@ -3983,48 +3930,23 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V4SI element from memory with constant element number.
-(define_insn_and_split "*vsx_extract_v4si_load"
- [(set (match_operand:SI 0 "register_operand" "=r,wa")
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0) (match_dup 4))]
-{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
-
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load")
- (set_attr "length" "8")])
-
-;; Extract a V8HI/V16QI element from memory with constant element number.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,v")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
-
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
[(set_attr "type" "load")
- (set_attr "length" "8")
- (set_attr "isa" "*,p9v"])
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work118)] Revert patches
@ 2023-04-14 10:55 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2023-04-14 10:55 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0190b0cbe6a26777cd605396de4e465bec821590
commit 0190b0cbe6a26777cd605396de4e465bec821590
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 14 06:55:33 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.cc | 54 ++++++++--------------------
gcc/config/rs6000/vsx.md | 88 ++++++---------------------------------------
2 files changed, 25 insertions(+), 117 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 0e2eb964783..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,9 +7686,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
/* All insns should use the 'Q' constraint (address is a single register) if
the element number is not a constant. */
gcc_assert (satisfies_constraint_Q (mem));
@@ -7707,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7753,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7778,7 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7791,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7851,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7861,39 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- /* If the final register is not the same mode because a FLOAT_EXTEND,
- ZERO_EXTEND, or SIGN_EXTEND was folded into the instruction, adjust
- the register to be of the correct mode for the load. */
- if (GET_MODE (scalar_reg) != scalar_mode)
- scalar_reg = gen_rtx_REG (scalar_mode, REGNO (scalar_reg));
-
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 6ed6eeecf80..d615474df01 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,8 +3549,7 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory with constant element number
-(define_insn_and_split "*vsx_extract_v4sf_load"
+(define_insn_and_split "*vsx_extract_v4sf_<mode>_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
(match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
@@ -3558,7 +3557,7 @@
(clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3568,27 +3567,6 @@
(set_attr "length" "8")
(set_attr "isa" "*,p7v,p9v,*")])
-;; V4SF extract from memory and convert to DFmode with constant element number
-(define_insn_and_split "*vsx_extract_v4sf_to_df_load"
- [(set (match_operand:DF 0 "register_operand" "=f,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p8v")])
-
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
@@ -3607,7 +3585,7 @@
DONE;
})
-;; V4SF extract from memory with variable element number
+;; Variable V4SF extract from memory
(define_insn_and_split "*vsx_extract_v4sf_var_load"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
@@ -3616,39 +3594,14 @@
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
-
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory and convert to DFmode with variable element number
-(define_insn_and_split "*vsx_extract_v4sf_to_df_var_load"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
-
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
@@ -3977,42 +3930,23 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V4SI element from memory with constant element number.
-(define_insn_and_split "*vsx_extract_v4si_load"
- [(set (match_operand:SI 0 "register_operand" "=r,wa")
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")])))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0) (match_dup 4))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "type" "load")
- (set_attr "length" "8")])
-
-;; Extract a V8HI/V16QI element from memory with constant element number.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,v")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
[(set_attr "type" "load")
- (set_attr "length" "8")
- (set_attr "isa" "*,p9v")])
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work118)] Revert patches
@ 2023-04-14 10:46 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2023-04-14 10:46 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8fb383d7d7373a7652fb710571d31b45a3acd2dd
commit 8fb383d7d7373a7652fb710571d31b45a3acd2dd
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 14 06:46:20 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 29 ++---------------------------
1 file changed, 2 insertions(+), 27 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 6ed6eeecf80..bbae9a1dffb 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3607,7 +3607,7 @@
DONE;
})
-;; V4SF extract from memory with variable element number
+;; Variable V4SF extract from memory
(define_insn_and_split "*vsx_extract_v4sf_var_load"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
@@ -3616,39 +3616,14 @@
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
-
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory and convert to DFmode with variable element number
-(define_insn_and_split "*vsx_extract_v4sf_to_df_var_load"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
-
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work118)] Revert patches
@ 2023-04-13 23:43 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2023-04-13 23:43 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:cc48f370255ca05015a903569bf6f1bddeb2c3c9
commit cc48f370255ca05015a903569bf6f1bddeb2c3c9
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 13 19:43:49 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.cc | 51 ++++++++++++-------------------------------
gcc/config/rs6000/vsx.md | 53 +++------------------------------------------
2 files changed, 17 insertions(+), 87 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 869a385eddf..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,9 +7686,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
/* All insns should use the 'Q' constraint (address is a single register) if
the element number is not a constant. */
gcc_assert (satisfies_constraint_Q (mem));
@@ -7750,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7775,7 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7788,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7848,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7858,39 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- /* If the final register is not the same mode because a FLOAT_EXTEND,
- ZERO_EXTEND, or SIGN_EXTEND was folded into the instruction, adjust
- the register to be of the correct mode for the load. */
- if (GET_MODE (scalar_reg) != scalar_mode)
- scalar_reg = gen_rtx_REG (scalar_mode, REGNO (scalar_reg));
-
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b46c4c8417d..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,7 +3549,6 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory with constant element number
(define_insn_and_split "*vsx_extract_v4sf_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
@@ -3558,7 +3557,7 @@
(clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3568,27 +3567,6 @@
(set_attr "length" "8")
(set_attr "isa" "*,p7v,p9v,*")])
-;; V4SF extract from memory and convert to DFmode with constant element number
-(define_insn_and_split "*vsx_extract_v4sf_to_df_load"
- [(set (match_operand:DF 0 "register_operand" "=f,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p8v")])
-
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
@@ -3607,7 +3585,7 @@
DONE;
})
-;; V4SF extract from memory with variable element number
+;; Variable V4SF extract from memory
(define_insn_and_split "*vsx_extract_v4sf_var_load"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
@@ -3616,39 +3594,14 @@
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
-
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory and convert to DFmode with variable element number
-(define_insn_and_split "*vsx_extract_v4sf_to_df_var_load"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
-
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work118)] Revert patches
@ 2023-04-13 15:47 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2023-04-13 15:47 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9ddd45773f0a3594f08ec7648fdbf6946d84460c
commit 9ddd45773f0a3594f08ec7648fdbf6946d84460c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 13 11:47:25 2023 -0400
Revert patches
Diff:
---
gcc/ChangeLog.meissner | 81 +---
gcc/config/rs6000/rs6000.cc | 13 +-
gcc/config/rs6000/vsx.md | 525 +--------------------
| 2 +-
| 6 +-
| 2 +-
6 files changed, 28 insertions(+), 601 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 069712f47dc..d216c9803f9 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,83 +1,4 @@
-==================== Branch work118, patch #1 ====================
-
-PR 93230: Fold sign/zero extension into vec_extract.
-
-gcc/
-
-2023-04-12 Michael Meissner <meissner@linux.ibm.com>
-
- PR target/93230
- * config/rs6000/rs6000.c (rs6000_split_vec_extract_var): Remove
- support for handling MEM, users call rs6000_adjust_vec_address
- directly.
- * config/rs6000/vsx.md (VSX_EX_FL): New mode attribute.
- (vsx_extract_v4sf_<mode>_load): Rename to vsx_extract_v4sf_load.
- (vsx_extract_v4sf_to_df_load): New insn to combine vec_extract of
- SFmode from memory being converted to DFmode.
- (vsx_extract_v4si_<su><mode>_load): New insn to support V4SI
- vec_extract from memory being converted to DImode directly without
- an extra sign/zero extension.
- (vsx_extract_v8hi_<su><mode>_load): New insn to support V8HI
- vec_extract from memory being converted to DImode directly without
- an extra sign/zero extension.
- (vsx_extract_v16qi_u<mode>_load): New insn to support V16QI
- vec_extract from memory being converted to DImode directly without
- an extra zero extension.
- (vsx_extract_v4si_var_load): Split V4SI extract from other small
- integers, and add support for loading up vector registers with
- sign/zero extension directly.
- (vsx_extract_<mode>_var_load, VSX_EXTRACT_I2 iterator): Split
- V8HI/V16QI vector extract from memory to handle loading vector
- registers in addition to GPR registers.
- (vsx_extract_<mode>_uns_di_var): New insn to optimize extracting a
- small integer from a vector in a register and zero extending it to
- DImode.
- (vsx_extract_v4si_<su><mode>_var_load): New insns to support
- combining a V4SI variable vector extract from memory with sign or
- zero extension.
- (vsx_extract_v8hi_<su><mode>_var_load): New insns to support
- combining a V8HI variable vector extract from memory with sign or
- zero extension.
- (vsx_extract_v4si_u<mode>_var_load): New insns to support
- combining a V16QI variable vector extract from memory with zero
- extension.
- (vsx_ext_v4si_fl_<mode>_load): New insn to support a V4SI vector
- extract that is converted to floating point to avoid doing a
- direct move.
- (vsx_ext_v4si_ufl_<mode>_load): New insn to support an unsigned
- V4SI vector extract that is converted to floating point to avoid
- doing a direct move.
- (vsx_ext_v4si_fl_<mode>_var_load): New insn to support a V4SI
- variable vector extract that is converted to floating point to
- avoid doing a direct move.
- (vsx_ext_v4si_ufl_<mode>_var_load): New insn to support an
- unsigned V4SI variable vector extract that is converted to
- floating point to avoid doing a direct move.
- (vsx_ext_<VSX_EXTRACT_I2:mode>_fl_<FL_CONV:mode>_load): New insns
- to support a V8HI/V16QI vector extract that is converted to
- floating point to avoid doing a direct move.
- (vsx_ext_<VSX_EXTRACT_I2:mode>_ufl_<FL_CONV:mode>_load): New insns
- to support an unsigned V8HI/V16QI vector extract that is converted
- to floating point to avoid doing a direct move.
- (vsx_ext_<VSX_EXTRACT_I2:mode>_fl_<FL_CONV:mode>_vl): New insns to
- support a variable V8HI/V16QI vector extract that is converted to
- floating point to avoid doing a direct move.
- (vsx_ext_<VSX_EXTRACT_I2:mode>_ufl_<FL_CONV:mode>_vl): New insns
- to support an unsigned variable V8HI/V16QI vector extract that is
- converted to floating point to avoid doing a direct move.
-
-gcc/testsuite/
-
-2023-04-12 Michael Meissner <meissner@linux.ibm.com>
-
- PR target/93230
- * gcc.target/powerpc/fold-vec-extract-char.p8.c: Adjust
- instruction counts.
- * gcc.target/powerpc/fold-vec-extract-int.p8.c: Adjust
- instruction counts.
- * gcc.target/powerpc/fold-vec-extract-short.p8.c: Adjust
- instruction counts.
- * gcc.target/powerpc/pcrel-opt-inc-di.c: Fix typo.
+==================== Branch work118, patch #22 was reverted ====================
==================== Branch work118, patch #21 ====================
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index b5eb8d7b2dd..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7886,7 +7886,18 @@ rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
gcc_assert (byte_shift >= 0);
- if (REG_P (src) || SUBREG_P (src))
+ /* If we are given a memory address, optimize to load just the element. We
+ don't have to adjust the vector element number on little endian
+ systems. */
+ if (MEM_P (src))
+ {
+ emit_move_insn (dest,
+ rs6000_adjust_vec_address (dest, src, element, tmp_gpr,
+ scalar_mode));
+ return;
+ }
+
+ else if (REG_P (src) || SUBREG_P (src))
{
int num_elements = GET_MODE_NUNITS (mode);
int bits_in_element = mode_to_bits (GET_MODE_INNER (mode));
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 981201db634..d615474df01 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -241,13 +241,6 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
-;; Mode attribute to give the constraint for the floating point type for vector
-;; extract and convert to floating point operations.
-(define_mode_attr VSX_EX_FL [(SF "wa")
- (DF "wa")
- (KF "v")
- (TF "v")])
-
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -3505,9 +3498,7 @@
DONE;
})
-;; Variable V2DI/V2DF extract from memory. We separate these insns, because
-;; the compiler will sometimes have the vector value in a register, but then
-;; decide the best way to do this is to do a store and then a load.
+;; Variable V2DI/V2DF extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=wa,r")
(unspec:<VEC_base> [(match_operand:VSX_D 1 "memory_operand" "Q,Q")
@@ -3558,7 +3549,7 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-(define_insn_and_split "*vsx_extract_v4sf_load"
+(define_insn_and_split "*vsx_extract_v4sf_<mode>_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
(match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
@@ -3576,29 +3567,7 @@
(set_attr "length" "8")
(set_attr "isa" "*,p7v,p9v,*")])
-;; V4SF extract to DFmode
-(define_insn_and_split "*vsx_extract_v4sf_to_df_load"
- [(set (match_operand:DF 0 "register_operand" "=f,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- rtx reg_sf = gen_rtx_REG (SFmode, reg_or_subregno (operands[0]));
- operands[4] = rs6000_adjust_vec_address (reg_sf, operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p8v")])
-
-;; Variable V4SF extract
+;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
(unspec:SF [(match_operand:V4SF 1 "gpc_reg_operand" "v")
@@ -3633,26 +3602,6 @@
}
[(set_attr "type" "fpload,load")])
-(define_insn_and_split "*vsx_extract_v4sf_to_df_var_load"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- rtx reg_sf = gen_rtx_REG (SFmode, reg_or_subregno (operands[0]));
- operands[4] = rs6000_adjust_vec_address (reg_sf, operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
@@ -3999,94 +3948,7 @@
[(set_attr "type" "load")
(set_attr "length" "8")])
-;; Optimize extracting and extending a single SI element from memory. GPRs
-;; take any address. If the element number is 0, we can use normal X-FORM
-;; (reg+reg) addressing to load up the vector register. Otherwise use Q to get
-;; a single register, so we can load the offset into the scratch register.
-(define_insn_and_split "*vsx_extract_v4si_<su><mode>_load"
- [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,wa,wa")
- (any_extend:EXTSI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,O,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:EXTSI (match_dup 4)))]
-{
- rtx reg_si = gen_rtx_REG (SImode, reg_or_subregno (operands[0]));
- operands[4] = rs6000_adjust_vec_address (reg_si, operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "type" "load,fpload,fpload")
- (set_attr "length" "8")])
-
-;; Optimize extracting and extending a single HI element from memory. GPRs
-;; take any address. If the element number is 0, we can use normal X-FORM
-;; (reg+reg) addressing to load up the vector register. Otherwise use Q to get
-;; a single register, so we can load the offset into the scratch register.
-(define_insn_and_split "*vsx_extract_v8hi_<su><mode>_load"
- [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,v,v")
- (any_extend:EXTHI
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_7_operand" "n,O,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:EXTHI (match_dup 4)))]
-{
- rtx reg_hi = gen_rtx_REG (HImode, reg_or_subregno (operands[0]));
- rtx mem = rs6000_adjust_vec_address (reg_hi, operands[1], operands[2],
- operands[3], HImode);
-
- /* We don't have a sign extend to a vector register, so we have to do
- the load first and then a sign extend operation. */
- if (int_reg_operand (operands[0], <MODE>mode) || <CODE> == ZERO_EXTEND)
- operands[4] = mem;
-
- else
- {
- emit_move_insn (reg_hi, mem);
- operands[4] = reg_hi;
- }
-}
- [(set_attr "type" "load,fpload,fpload")
- (set_attr "length" "8,12,12")
- (set_attr "isa" "*,p9v,p9v")])
-
-;; Optimize extracting and zero extending a single QI element from memory.
-;; GPRs take any address. If the element number is 0, we can use normal X-FORM
-;; (reg+reg) addressing to load up the vector register. Otherwise use Q to get
-;; a single register, so we can load the offset into the scratch register. We
-;; don't have eiter a GPR load or a vector load that does sign extension, so
-;; only do the zero_extend case.
-(define_insn_and_split "*vsx_extract_v16qi_u<mode>_load"
- [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,v,v")
- (zero_extend:EXTQI
- (vec_select:QI
- (match_operand:V16QI 1 "memory_operand" "m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_15_operand" "n,O,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b,&b"))]
- "VECTOR_MEM_VSX_P (V16QImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:EXTQI (match_dup 4)))]
-{
- rtx reg_qi = gen_rtx_REG (QImode, reg_or_subregno (operands[0]));
- operands[4] = rs6000_adjust_vec_address (reg_qi, operands[1], operands[2],
- operands[3], QImode);
-}
- [(set_attr "type" "load,fpload,fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p9v,p9v")])
-
-;; Variable V16QI/V8HI/V4SI extract
+;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
(unspec:<VEC_base>
@@ -4106,33 +3968,14 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V4SI extract when the vector is in memory
-(define_insn_and_split "*vsx_extract_v4si_var_load"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,wa")
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0) (match_dup 4))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "type" "load")
- (set_attr "length" "8")])
-
-;; Variable V16QI/V8HI extract from memory
+;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,v")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
@@ -4141,113 +3984,7 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load")
- (set_attr "length" "8")
- (set_attr "isa" "*,p9v")])
-
-;; Variable V4SI/V8HI/V16QI vector extract when the vector is in a register and
-;; combine with zero extend
-(define_insn_and_split "*vsx_extract_<mode>_uns_di_var"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI
- (unspec:<VSX_EXTRACT_I:VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "v,v")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=r,r"))
- (clobber (match_scratch:V2DI 4 "=X,&v"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- machine_mode smode = <VEC_base>mode;
- rtx reg_small = gen_rtx_REG (smode, REGNO (operands[0]));
- rs6000_split_vec_extract_var (reg_small, operands[1], operands[2],
- operands[3], operands[4]);
- DONE;
-}
- [(set_attr "isa" "p9v,*")])
-
-;; Variable V4SI vector extract when the vector is in memory, and combine with
-;; a sign or zero extend.
-(define_insn_and_split "*vsx_extract_v4si_<su><mode>_var_load"
- [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,wa")
- (any_extend:EXTSI
- (unspec:V4SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:EXTSI (match_dup 4)))]
-{
- rtx reg_si = gen_rtx_REG (SImode, REGNO (operands[0]));
- operands[4] = rs6000_adjust_vec_address (reg_si, operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "length" "8")])
-
-;; Variable V8HI vector extract when the vector is in memory, and combine with
-;; a sign or zero extend.
-(define_insn_and_split "*vsx_extract_v8hi_<su><mode>_var_load"
- [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,v")
- (any_extend:EXTHI
- (unspec:V8HI
- [(match_operand:V8HI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:EXTHI (match_dup 4)))]
-{
- rtx reg_hi = gen_rtx_REG (HImode, REGNO (operands[0]));
- rtx mem = rs6000_adjust_vec_address (reg_hi, operands[1], operands[2],
- operands[3], HImode);
-
- /* Altivec load HImode does not have a sign extend version. */
- if (int_reg_operand (operands[0], HImode) || <CODE> == ZERO_EXTEND)
- operands[4] = mem;
- else
- {
- emit_move_insn (reg_hi, mem);
- operands[4] = reg_hi;
- }
-}
- [(set_attr "type" "load,fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p9v")])
-
-;; Variable V16QI vector extract when the vector is in memory, and combine with
-;; a zero extend. There is no sign extend version of load byte.
-(define_insn_and_split "*vsx_extract_v4si_u<mode>_var_load"
- [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,wa")
- (any_extend:EXTQI
- (unspec:V16QI
- [(match_operand:V16QI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V16QImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:EXTQI (match_dup 4)))]
-{
- rtx reg_qi = gen_rtx_REG (QImode, REGNO (operands[0]));
- operands[4] = rs6000_adjust_vec_address (reg_qi, operands[1], operands[2],
- operands[3], QImode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p9v")])
+ [(set_attr "type" "load")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
@@ -4619,248 +4356,6 @@
}
[(set_attr "isa" "<FL_CONV:VSisa>")])
-;; Optimize <type> f = (<ftype>) vec_extract (V4SI, <n>).
-;;
-;; <ftype> is a hardware floating point type that conversions are directly
-;; supported (SFmode, DFmode, KFmode, maybe TFmode).
-;;
-;; The element number (<n>) is constant.
-;;
-;; The vector is in memory, and we convert the vector extraction to a load to
-;; the VSX registers and then convert, avoiding a direct move.
-;;
-;; For SFmode/DFmode, we can use all vector registers. For KFmode/TFmode, we
-;; have to use only the Altivec regsiters.
-(define_insn_and_split "*vsx_ext_v4si_fl_<mode>_load"
- [(set (match_operand:FL_CONV 0 "gpc_reg_operand" "=<VSX_EX_FL>,<VSX_EX_FL>")
- (float:FL_CONV
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (sign_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:<FL_CONV:MODE> (match_dup 4)))]
-{
- rtx reg_si = gen_rtx_REG (SImode, reg_or_subregno (operands[0]));
- operands[4] = gen_rtx_REG (DImode, reg_or_subregno (operands[0]));
- operands[5] = rs6000_adjust_vec_address (reg_si, operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "isa" "<FL_CONV:VSisa>")])
-
-(define_insn_and_split "*vsx_ext_v4si_ufl_<mode>_load"
- [(set (match_operand:FL_CONV 0 "gpc_reg_operand" "=<VSX_EX_FL>,<VSX_EX_FL>")
- (unsigned_float:FL_CONV
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (unsigned_float:<FL_CONV:MODE> (match_dup 4)))]
-{
- rtx reg_si = gen_rtx_REG (SImode, reg_or_subregno (operands[0]));
- operands[4] = gen_rtx_REG (DImode, reg_or_subregno (operands[0]));
- operands[5] = rs6000_adjust_vec_address (reg_si, operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "isa" "<FL_CONV:VSisa>")])
-
-;; Optimize <type> f = (<ftype>) vec_extract (V4SI, <n>).
-;;
-;; <ftype> is a hardware floating point type that conversions are directly
-;; supported (SFmode, DFmode, KFmode, maybe TFmode).
-;;
-;; The element number (<n>) is variable.
-;;
-;; The vector is in memory, and we convert the vector extraction to a load to
-;; the VSX registers and then convert, avoiding a direct move.
-;;
-;; For SFmode/DFmode, we can use all vector registers. For KFmode/TFmode, we
-;; have to use only the Altivec regsiters.
-(define_insn_and_split "*vsx_ext_v4si_fl_<mode>_var_load"
- [(set (match_operand:FL_CONV 0 "gpc_reg_operand" "=<VSX_EX_FL>")
- (float:FL_CONV
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (sign_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:<FL_CONV:MODE> (match_dup 4)))]
-{
- rtx reg_si = gen_rtx_REG (SImode, reg_or_subregno (operands[0]));
- operands[4] = gen_rtx_REG (DImode, reg_or_subregno (operands[0]));
- operands[5] = rs6000_adjust_vec_address (reg_si, operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "isa" "<FL_CONV:VSisa>")])
-
-(define_insn_and_split "*vsx_ext_v4si_ufl_<mode>_var_load"
- [(set (match_operand:FL_CONV 0 "gpc_reg_operand" "=<VSX_EX_FL>")
- (unsigned_float:FL_CONV
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (unsigned_float:<FL_CONV:MODE> (match_dup 4)))]
-{
- rtx reg_si = gen_rtx_REG (SImode, reg_or_subregno (operands[0]));
- operands[4] = gen_rtx_REG (DImode, reg_or_subregno (operands[0]));
- operands[5] = rs6000_adjust_vec_address (reg_si, operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "isa" "<FL_CONV:VSisa>")])
-
-;; Optimize <type> f = (<ftype>) vec_extract (V8HI/V16QI, <n>).
-;;
-;; <ftype> is a hardware floating point type that conversions are directly
-;; supported (SFmode, DFmode, KFmode, maybe TFmode).
-;;
-;; The element number (<n>) is constant.
-;;
-;; The vector is in memory, and we convert the vector extraction to a load to
-;; the VSX registers and then convert, avoiding a direct move.
-;;
-;; For SFmode/DFmode, we can use all vector registers. For KFmode/TFmode, we
-;; have to use only the Altivec regsiters.
-(define_insn_and_split "*vsx_ext_<VSX_EXTRACT_I2:mode>_fl_<FL_CONV:mode>_load"
- [(set (match_operand:FL_CONV 0 "gpc_reg_operand"
- "=<FL_CONV:VSX_EX_FL>,<FL_CONV:VSX_EX_FL>")
- (float:FL_CONV
- (vec_select:<VSX_EXTRACT_I2:VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "O,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b"))
- (clobber (match_scratch:DI 4 "=v,v"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_POWERPC64
- && TARGET_P9_VECTOR"
- "#"
- "&& reload_completed"
- [(set (match_dup 5)
- (match_dup 6))
- (set (match_dup 4)
- (sign_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:<FL_CONV:MODE> (match_dup 4)))]
-{
- machine_mode smode = <VSX_EXTRACT_I2:VEC_base>mode;
- operands[5] = gen_rtx_REG (smode, reg_or_subregno (operands[4]));
- operands[6] = rs6000_adjust_vec_address (operands[5], operands[1],
- operands[2], operands[3],
- smode);
-})
-
-(define_insn_and_split "*vsx_ext_<VSX_EXTRACT_I2:mode>_ufl_<FL_CONV:mode>_load"
- [(set (match_operand:FL_CONV 0 "gpc_reg_operand"
- "=<FL_CONV:VSX_EX_FL>,<FL_CONV:VSX_EX_FL>")
- (unsigned_float:FL_CONV
- (vec_select:<VSX_EXTRACT_I2:VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "O,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_POWERPC64
- && TARGET_P9_VECTOR"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (unsigned_float:<FL_CONV:MODE> (match_dup 4)))]
-{
- machine_mode smode = <VSX_EXTRACT_I2:VEC_base>mode;
- rtx reg_small = gen_rtx_REG (smode, reg_or_subregno (operands[0]));
- operands[4] = gen_rtx_REG (DImode, reg_or_subregno (operands[0]));
- operands[5] = rs6000_adjust_vec_address (reg_small, operands[1],
- operands[2], operands[3],
- smode);
-})
-
-;; Optimize <type> f = (<ftype>) vec_extract (V8HI/V16QI, <n>).
-;;
-;; <ftype> is a hardware floating point type that conversions are directly
-;; supported (SFmode, DFmode, KFmode, maybe TFmode).
-;;
-;; The element number (<n>) is variable.
-;;
-;; The vector is in memory, and we convert the vector extraction to a load to
-;; the VSX registers and then convert, avoiding a direct move.
-;;
-;; For SFmode/DFmode, we can use all vector registers. For KFmode/TFmode, we
-;; have to use only the Altivec regsiters.
-(define_insn_and_split "*vsx_ext_<VSX_EXTRACT_I2:mode>_fl_<FL_CONV:mode>_vl"
- [(set (match_operand:FL_CONV 0 "gpc_reg_operand" "=<FL_CONV:VSX_EX_FL>")
- (float:FL_CONV
- (unspec:<VSX_EXTRACT_I2:VEC_base>
- [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=v"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_POWERPC64
- && TARGET_P9_VECTOR"
- "#"
- "&& reload_completed"
- [(set (match_dup 5)
- (match_dup 6))
- (set (match_dup 4)
- (sign_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:<FL_CONV:MODE> (match_dup 4)))]
-{
- machine_mode smode = <VSX_EXTRACT_I2:VEC_base>mode;
- operands[5] = gen_rtx_REG (smode, reg_or_subregno (operands[4]));
- operands[6] = rs6000_adjust_vec_address (operands[5], operands[1],
- operands[2], operands[3],
- smode);
-})
-
-(define_insn_and_split "*vsx_ext_<VSX_EXTRACT_I2:mode>_ufl_<FL_CONV:mode>_vl"
- [(set (match_operand:FL_CONV 0 "gpc_reg_operand" "=<FL_CONV:VSX_EX_FL>")
- (unsigned_float:FL_CONV
- (unspec:<VSX_EXTRACT_I2:VEC_base>
- [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_POWERPC64
- && TARGET_P9_VECTOR"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (unsigned_float:<FL_CONV:MODE> (match_dup 4)))]
-{
- machine_mode smode = <VSX_EXTRACT_I2:VEC_base>mode;
- rtx reg_small = gen_rtx_REG (smode, reg_or_subregno (operands[0]));
- operands[4] = gen_rtx_REG (DImode, reg_or_subregno (operands[0]));
- operands[5] = rs6000_adjust_vec_address (reg_small, operands[1],
- operands[2], operands[3],
- smode);
-})
-
;; V4SI/V8HI/V16QI set operation on ISA 3.0
(define_insn "vsx_set_<mode>_p9"
[(set (match_operand:VSX_EXTRACT_I 0 "gpc_reg_operand" "=<VSX_EX>")
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p8.c
index 555be18a3ea..f3b9556b2e6 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p8.c
@@ -21,7 +21,7 @@
/* { dg-final { scan-assembler-times {\msrdi\M} 3 { target lp64 } } } */
/* { dg-final { scan-assembler-times "extsb" 2 } } */
/* { dg-final { scan-assembler-times {\mvspltb\M} 3 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\mrlwinm\M} 2 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mrlwinm\M} 4 { target lp64 } } } */
/* multiple codegen variations for -m32. */
/* { dg-final { scan-assembler-times {\mrlwinm\M} 3 { target ilp32 } } } */
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
index c9e9a26ab06..75eaf25943b 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
@@ -7,14 +7,14 @@
// Targeting P8 (LE) and (BE). 6 tests total.
// P8 LE constant: vspltw, mfvsrwz, (1:extsw/2:rldicl)
-// P8 LE variables: subfic, sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, (1:extsw/2:rldicl))
+// P8 LE variables: subfic, sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, (1:extsw/5:rldicl))
// P8 BE constant: vspltw, mfvsrwz, (1:extsw/2:rldicl)
// P8 BE variables: sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, (1:extsw/2:rldicl))
/* { dg-final { scan-assembler-times {\mvspltw\M} 3 { target lp64 } } } */
/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 3 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 5 { target { le } } } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 { target { lp64 && be } } } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 7 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 4 { target { lp64 && be } } } } */
/* { dg-final { scan-assembler-times {\msubfic\M} 3 { target { le } } } } */
/* { dg-final { scan-assembler-times {\msldi\M} 3 { target lp64 } } } */
/* { dg-final { scan-assembler-times {\mmtvsrd\M} 3 { target lp64 } } } */
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
index 2daebb86f21..0ddecb4e4b5 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
@@ -24,7 +24,7 @@
/* { dg-final { scan-assembler-times "mfvsrd" 6 { target lp64 } } } */
/* { dg-final { scan-assembler-times "srdi" 3 { target lp64 } } } */
/* { dg-final { scan-assembler-times "extsh" 2 { target lp64 } } } */
-/* { dg-final { scan-assembler-times "rlwinm" 2 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "rlwinm" 4 { target lp64 } } } */
/* -m32 codegen tests. */
/* { dg-final { scan-assembler-times {\mli\M} 6 { target ilp32 } } } */
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work118)] Revert patches
@ 2023-04-12 22:10 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2023-04-12 22:10 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:458a7dd44a5db45facc30a802442b0427299f8d5
commit 458a7dd44a5db45facc30a802442b0427299f8d5
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 12 18:10:02 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.md | 52 ------------------
gcc/config/rs6000/vsx.md | 18 -------
gcc/testsuite/gcc.target/powerpc/pr99293.c | 21 --------
.../gcc.target/powerpc/zero-extend-di-ti.c | 62 ----------------------
4 files changed, 153 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7d6c94aee5b..0e1f4cb3868 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -986,58 +986,6 @@
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_insn_and_split "zero_extendditi2"
- [(set (match_operand:TI 0 "gpc_reg_operand" "=r,r,wa,wa,wa")
- (zero_extend:TI
- (match_operand:DI 1 "reg_or_mem_operand" "r,m,b,Z,wa")))
- (clobber (match_scratch:DI 2 "=&X,X,X,X,wa"))]
- "TARGET_POWERPC64 && TARGET_P9_VECTOR"
- "@
- #
- #
- mtvsrdd %x0,0,%1
- lxvrdx %x0,%y1
- #"
- "&& reload_completed
- && (int_reg_operand (operands[0], TImode)
- || (vsx_register_operand (operands[0], TImode)
- && vsx_register_operand (operands[1], DImode)))"
- [(set (match_dup 2) (match_dup 1))
- (set (match_dup 3) (const_int 0))]
-{
- rtx dest = operands[0];
- rtx src = operands[1];
-
- /* If we are converting a VSX DImode to VSX TImode, we need to move the upper
- 64-bits (DImode) to the lower 64-bits. We can't just do a xxpermdi
- instruction to swap the two 64-bit words, because can't rely on the bottom
- 64-bits of the VSX register being 0. Instead we create a 0 and do the
- xxpermdi operation to combine the two registers. */
- if (vsx_register_operand (dest, TImode)
- && vsx_register_operand (src, DImode))
- {
- rtx tmp = operands[2];
- emit_move_insn (tmp, const0_rtx);
-
- rtx hi = tmp;
- rtx lo = src;
- if (!BYTES_BIG_ENDIAN)
- std::swap (hi, lo);
-
- rtx dest_v2di = gen_rtx_REG (V2DImode, reg_or_subregno (dest));
- emit_insn (gen_vsx_concat_v2di (dest_v2di, hi, lo));
- DONE;
- }
-
- /* If we are zero extending to a GPR register either from a GPR register,
- a VSX register or from memory, do the zero extend operation to the
- lower DI register, and set the upper DI register to 0. */
- operands[2] = gen_lowpart (DImode, dest);
- operands[3] = gen_highpart (DImode, dest);
-}
- [(set_attr "type" "*,load,vecexts,vecload,vecperm")
- (set_attr "isa" "*,*,p9v,p10,*")
- (set_attr "length" "8,8,*,*,8")])
(define_insn "extendqi<mode>2"
[(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*v")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d615474df01..7d845df5c2d 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4573,24 +4573,6 @@
"lxvdsx %x0,%y1"
[(set_attr "type" "vecload")])
-;; Optimize SPLAT of an extract from a V2DF/V2DI vector with a constant element
-(define_insn "*vsx_splat_extract_<mode>"
- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
- (vec_duplicate:VSX_D
- (vec_select:<VEC_base>
- (match_operand:VSX_D 1 "vsx_register_operand" "wa")
- (parallel [(match_operand 2 "const_0_to_1_operand" "n")]))))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
-{
- int which_word = INTVAL (operands[2]);
- if (!BYTES_BIG_ENDIAN)
- which_word = 1 - which_word;
-
- operands[3] = GEN_INT (which_word ? 3 : 0);
- return "xxpermdi %x0,%x1,%x1,%3";
-}
- [(set_attr "type" "vecperm")])
-
;; V4SI splat support
(define_insn "vsx_splat_v4si"
[(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr99293.c b/gcc/testsuite/gcc.target/powerpc/pr99293.c
deleted file mode 100644
index 582bebb88ef..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr99293.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* Test for PR 99263, which wants to do:
- __builtin_vec_splats (__builtin_vec_extract (v, n))
-
- where v is a V2DF or V2DI vector and n is either 0 or 1. Previously the
- compiler would do a direct move to the GPR registers to select the item and a
- direct move from the GPR registers to do the splat. */
-
-vector long long splat_dup_l_0 (vector long long v)
-{
- return __builtin_vec_splats (__builtin_vec_extract (v, 0));
-}
-
-vector long long splat_dup_l_1 (vector long long v)
-{
- return __builtin_vec_splats (__builtin_vec_extract (v, 1));
-}
-
-/* { dg-final { scan-assembler-times "xxpermdi" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/zero-extend-di-ti.c b/gcc/testsuite/gcc.target/powerpc/zero-extend-di-ti.c
deleted file mode 100644
index 9b3b9c4dbd0..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/zero-extend-di-ti.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-require-effective-target int128 } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* This patch makes sure the various optimization and code paths are done for
- zero extending DImode to TImode on power10. */
-
-__uint128_t
-gpr_to_gpr (unsigned long long a)
-{
- /* li 4,0. */
- return a;
-}
-
-__uint128_t
-mem_to_gpr (unsigned long long *p)
-{
- /* ld 3,0(3); li 4,0. */
- return *p;
-}
-
-__uint128_t
-vsx_to_gpr (__uint128_t *p, double d)
-{
- /* fctiduz 1,1; li 4,0;mfvsrd 3,1. */
- return (unsigned long long)d;
-}
-
-void
-gpr_to_vsx (__uint128_t *p, unsigned long long a)
-{
- /* mtvsrdd 0,0,4; stxv 0,0(3). */
- __uint128_t b = a;
- __asm__ (" # %x0" : "+wa" (b));
- *p = b;
-}
-
-void
-mem_to_vsx (__uint128_t *p, unsigned long long *q)
-{
- /* lxvrdx 0,0,4; stxv 0,0(3). */
- __uint128_t a = *q;
- __asm__ (" # %x0" : "+wa" (a));
- *p = a;
-}
-
-void
-vsx_to_vsx (__uint128_t *p, double d)
-{
- /* fctiduz 1,1; xxspltib 0,0; xxpermdi 0,0,1,0; stxv 0,0(3). */
- __uint128_t a = (unsigned long long)d;
- __asm__ (" # %x0" : "+wa" (a));
- *p = a;
-}
-
-/* { dg-final { scan-assembler-times {\mli\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mld\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlxvrdx\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mmfvsrd\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mmtvsrdd\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mstxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work118)] Revert patches
@ 2023-04-11 23:11 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2023-04-11 23:11 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a305c07ee0a5f9a3ab583a60894f962c3b98238d
commit a305c07ee0a5f9a3ab583a60894f962c3b98238d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 11 19:11:01 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 18 ------------------
gcc/testsuite/gcc.target/powerpc/pr99293.c | 21 ---------------------
2 files changed, 39 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d615474df01..7d845df5c2d 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4573,24 +4573,6 @@
"lxvdsx %x0,%y1"
[(set_attr "type" "vecload")])
-;; Optimize SPLAT of an extract from a V2DF/V2DI vector with a constant element
-(define_insn "*vsx_splat_extract_<mode>"
- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
- (vec_duplicate:VSX_D
- (vec_select:<VEC_base>
- (match_operand:VSX_D 1 "vsx_register_operand" "wa")
- (parallel [(match_operand 2 "const_0_to_1_operand" "n")]))))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
-{
- int which_word = INTVAL (operands[2]);
- if (!BYTES_BIG_ENDIAN)
- which_word = 1 - which_word;
-
- operands[3] = GEN_INT (which_word ? 3 : 0);
- return "xxpermdi %x0,%x1,%x1,%3";
-}
- [(set_attr "type" "vecperm")])
-
;; V4SI splat support
(define_insn "vsx_splat_v4si"
[(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr99293.c b/gcc/testsuite/gcc.target/powerpc/pr99293.c
deleted file mode 100644
index 582bebb88ef..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr99293.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* Test for PR 99263, which wants to do:
- __builtin_vec_splats (__builtin_vec_extract (v, n))
-
- where v is a V2DF or V2DI vector and n is either 0 or 1. Previously the
- compiler would do a direct move to the GPR registers to select the item and a
- direct move from the GPR registers to do the splat. */
-
-vector long long splat_dup_l_0 (vector long long v)
-{
- return __builtin_vec_splats (__builtin_vec_extract (v, 0));
-}
-
-vector long long splat_dup_l_1 (vector long long v)
-{
- return __builtin_vec_splats (__builtin_vec_extract (v, 1));
-}
-
-/* { dg-final { scan-assembler-times "xxpermdi" 2 } } */
^ permalink raw reply [flat|nested] 7+ messages in thread
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