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* [gcc(refs/users/meissner/heads/work118)] Allow vec_extract of int vectors to vector registers
@ 2023-04-14 15:13 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-14 15:13 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:474ed743b35ae8b359be94c51af4014176cb31d7
commit 474ed743b35ae8b359be94c51af4014176cb31d7
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 14 11:13:04 2023 -0400
Allow vec_extract of int vectors to vector registers
2023-04-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load): New insn, split off from
vsx_extract_<mode>_load to handle loading SImode into vector registers
from V4SImode.
(vsx_extract_<mode>_load): Restrict to V8HI and V16QI. Add support to
load the element into vector registers.
Diff:
---
gcc/config/rs6000/vsx.md | 33 ++++++++++++++++++++++++++-------
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c1cbdbe5391..a145ae6ca3e 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3971,13 +3971,31 @@
}
[(set_attr "type" "mfvsr")])
-;; Optimize extracting a single scalar element from memory.
+;; Extract a V4SI element from memory with constant element number.
+(define_insn_and_split "*vsx_extract_v4si_load"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,wa,wa")
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,m,Z,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")])))
+ (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (match_dup 4))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], SImode);
+}
+ [(set_attr "type" "load,load,fpload,fpload")
+ (set_attr "length" "4,8,4,8")])
+
+;; Extract a V8HI/V16QI element from memory with constant element number.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m,Z,Q")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,0,n")])))
+ (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
@@ -3986,8 +4004,9 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load")
- (set_attr "length" "8")])
+ [(set_attr "type" "load,load,fpload,fpload")
+ (set_attr "length" "4,8,4,8")
+ (set_attr "isa" "*,*,p9v,p9v")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work118)] Allow vec_extract of int vectors to vector registers
@ 2023-04-14 19:00 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-14 19:00 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:de7db33792cdd5fa8ab7c825ece2bdbc56e8d477
commit de7db33792cdd5fa8ab7c825ece2bdbc56e8d477
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 14 15:00:14 2023 -0400
Allow vec_extract of int vectors to vector registers
2023-04-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load): New insn, split off from
vsx_extract_<mode>_load to handle loading SImode into vector registers
from V4SImode.
(vsx_extract_<mode>_load): Restrict to V8HI and V16QI. Add support to
load the element into vector registers.
Diff:
---
gcc/config/rs6000/vsx.md | 33 ++++++++++++++++++++++++++-------
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c1cbdbe5391..a145ae6ca3e 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3971,13 +3971,31 @@
}
[(set_attr "type" "mfvsr")])
-;; Optimize extracting a single scalar element from memory.
+;; Extract a V4SI element from memory with constant element number.
+(define_insn_and_split "*vsx_extract_v4si_load"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,wa,wa")
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,m,Z,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")])))
+ (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (match_dup 4))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], SImode);
+}
+ [(set_attr "type" "load,load,fpload,fpload")
+ (set_attr "length" "4,8,4,8")])
+
+;; Extract a V8HI/V16QI element from memory with constant element number.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m,Z,Q")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,0,n")])))
+ (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
@@ -3986,8 +4004,9 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load")
- (set_attr "length" "8")])
+ [(set_attr "type" "load,load,fpload,fpload")
+ (set_attr "length" "4,8,4,8")
+ (set_attr "isa" "*,*,p9v,p9v")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work118)] Allow vec_extract of int vectors to vector registers
@ 2023-04-14 0:31 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-14 0:31 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:62e3f45ac4e4ce44acda8a9324a7726e3a735fb1
commit 62e3f45ac4e4ce44acda8a9324a7726e3a735fb1
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 13 20:30:42 2023 -0400
Allow vec_extract of int vectors to vector registers
2023-04-13 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load): New insn, split off from
vsx_extract_<mode>_load to handle loading SImode into vector registers
from V4SImode.
(vsx_extract_<mode>_load): Restrict to V8HI and V16QI. Allow splitting
before reload. Add support to load the element into vector registers.
Diff:
---
gcc/config/rs6000/vsx.md | 33 ++++++++++++++++++++++++++-------
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b46c4c8417d..6ed6eeecf80 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3977,23 +3977,42 @@
}
[(set_attr "type" "mfvsr")])
-;; Optimize extracting a single scalar element from memory.
+;; Extract a V4SI element from memory with constant element number.
+(define_insn_and_split "*vsx_extract_v4si_load"
+ [(set (match_operand:SI 0 "register_operand" "=r,wa")
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")])))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0) (match_dup 4))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], SImode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
+;; Extract a V8HI/V16QI element from memory with constant element number.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r,v")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
[(set_attr "type" "load")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "isa" "*,p9v")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work118)] Allow vec_extract of int vectors to vector registers
@ 2023-04-13 18:38 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-13 18:38 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d4b729d2e55d9eca76812cd235e1d0ffdaf0d137
commit d4b729d2e55d9eca76812cd235e1d0ffdaf0d137
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 13 14:37:53 2023 -0400
Allow vec_extract of int vectors to vector registers
2023-04-13 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load): New insn.
(sx_extract_<mode>_load): Restrict to V8HI and V16QI. Allow splitting
before reload. Add support to load the element into vector registers.
Diff:
---
gcc/config/rs6000/vsx.md | 37 +++++++++++++++++++++++++++++++------
1 file changed, 31 insertions(+), 6 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d4386cb5028..fc7dd63ff3f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3983,23 +3983,48 @@
}
[(set_attr "type" "mfvsr")])
-;; Optimize extracting a single scalar element from memory.
+;; Extract a V4SI element from memory with constant element number.
+(define_insn_and_split "*vsx_extract_v4si_load"
+ [(set (match_operand:SI 0 "register_operand" "=r,wa")
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0) (match_dup 4))]
+{
+ if (GET_CODE (operands[3]) == SCRATCH)
+ operands[3] = gen_reg_rtx (DImode);
+
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
+;; Extract a V8HI/V16QI element from memory with constant element number.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r,v")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
+ if (GET_CODE (operands[3]) == SCRATCH)
+ operands[3] = gen_reg_rtx (DImode);
+
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
[(set_attr "type" "load")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "isa" "*,p9v"])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
^ permalink raw reply [flat|nested] 4+ messages in thread
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