[gcc(refs/users/meissner/heads/work118)] Update ChangeLog.*

[gcc(refs/users/meissner/heads/work118)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:46635f2706353c0e8c476e09b5a5fea54366ba79

commit 46635f2706353c0e8c476e09b5a5fea54366ba79
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 14 12:44:16 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 90 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index d216c9803f9..71bb4d6e9d9 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,93 @@
+==================== Branch work118, patch #54 ====================
+
+Add conversions fro V4SI vec_extract
+
+This patch adds combiner insns to fold in sign and zero extension of vec_extract
+of V4SI with a constant element when expanding to DImode.  It also adds in
+combiner insns to create SFmdoe and DFmode.
+
+2023-04-14   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
+	(vsx_extract_v4si_load_to_<mode>): New insn.
+	(vsx_extract_v4si_load_to_uns<mode>): New insn.
+
+==================== Branch work118, patch #53 ====================
+
+Allow vec_extract of int vectors to vector registers
+
+2023-04-14   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4si_load): New insn, split off from
+	vsx_extract_<mode>_load to handle loading SImode into vector registers
+	from V4SImode.
+	(vsx_extract_<mode>_load): Restrict to V8HI and V16QI.  Add support to
+	load the element into vector registers.
+
+==================== Branch work118, patch #52 ====================
+
+Improve vec_extract of V4SF from memory with variable element.
+
+2023-04-14   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
+	register allocation.
+	(vsx_extract_v4sf_to_df_var_load): New insn.
+
+
+==================== Branch work118, patch #51 ====================
+
+Improve vec_extract of V4SF from memory with constant element.
+
+2023-04-14   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.cc (get_vector_offset): Allow being called before
+	register allocation.
+	(adjust_vec_address_pcrel): Likewise.
+	(rs6000_adjust_vec_address): Likewise.
+	* config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before
+	register allocation.
+	(vsx_extract_v4sf_to_df_load): New insn.
+
+==================== Branch work118, patch #50 ====================
+
+Fix typo in insn name.
+
+In doing other work, I noticed that there was an insn:
+
+	vsx_extract_v4sf_<mode>_load
+
+Which did not have an iterator.  I removed the useless <mode>.
+
+2023-04-14   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4sf_load): Rename from
+	vsx_extract_v4sf_<mode>_load.
+
+==================== Branch work118, patch #42 was reverted ====================
+
+==================== Branch work118, patch #41 was reverted ====================
+
+==================== Branch work118, patch #40 was reverted ====================
+
+==================== Branch work118, patch #33 was reverted ====================
+
+==================== Branch work118, patch #32 was reverted ====================
+
+==================== Branch work118, patch #31 was reverted ====================
+
+==================== Branch work118, patch #30 was reverted ====================
+
 ==================== Branch work118, patch #22 was reverted ====================
 
 ==================== Branch work118, patch #21 ====================

[gcc(refs/users/meissner/heads/work118)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:1c5a1f92d5fe0df711284b7aeff0067f008e9b25

commit 1c5a1f92d5fe0df711284b7aeff0067f008e9b25
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 14 23:22:08 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 78 +++++++++++++++++++++++++++++---------------------
 1 file changed, 46 insertions(+), 32 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 2cd1d02b800..cbfd39835fc 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,35 +1,27 @@
-==================== Branch work118, patch #55 ====================
+==================== Branch work118, patch #67 was reverted ====================
 
-Add sign/zero extension to vec_extract with variable element number.
+==================== Branch work118, patch #66 was reverted ====================
 
-2023-04-14   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
+==================== Branch work118, patch #65 ====================
 
-	* config/rs6000/vsx.md (VSX_EXTRACT_SIGN): New iterator.
-	(vsx_extract_<mode>_var_load): Update length.
-	(vsx_extract_<mode>_var_load_to_sdi): New insn.
-	(vsx_extract_<mode>_var_load_to_udi): New insn.
+Add float/double conversions fro V4SI vec_extract
 
-==================== Branch work118, patch #54 ====================
-
-Add conversions fro V4SI vec_extract
-
-This patch adds combiner insns to fold in sign and zero extension of vec_extract
-of V4SI with a constant element when expanding to DImode.  It also adds in
-combiner insns to create SFmdoe and DFmode.
+This patch adds combiner insns to fold in conversion to float or double (both
+signed and unsigned) of V4SI vec_extract with a constant element.  With this
+patch, GCC will load the SImode value directly into the vector register with
+LFIWZX or LFIWAX instead of doing a LWZ and then moving the value over with a
+direct move before the floating point conversion.
 
 2023-04-14   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
-	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
-	(vsx_extract_v4si_load_to_<mode>): New insn.
-	(vsx_extract_v4si_load_to_uns<mode>): New insn.
+	* config/rs6000/rs6000.md (SIGN_ZERO): New code attribute.
+	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<mode>): New insn.
 
-==================== Branch work118, patch #53 ====================
+==================== Branch work118, patch #64 ====================
 
-Allow vec_extract of int vectors to vector registers
+Allow vec_extract of int vectors to target vector registers
 
 2023-04-14   Michael Meissner  <meissner@linux.ibm.com>
 
@@ -41,22 +33,35 @@ gcc/
 	(vsx_extract_<mode>_load): Restrict to V8HI and V16QI.  Add support to
 	load the element into vector registers.
 
-==================== Branch work118, patch #52 ====================
+==================== Branch work118, patch #63 ====================
+
+Add double convert combiner to vsx_extract for variable index.
 
-Improve vec_extract of V4SF from memory with variable element.
+This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
+where the element number is variable combined with a conversion to DFmode.
 
 2023-04-14   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
-	* config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
-	register allocation.
-	(vsx_extract_v4sf_to_df_var_load): New insn.
+	* config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.
 
+==================== Branch work118, patch #62 ====================
 
-==================== Branch work118, patch #51 ====================
+Add double convert combiner to vsx_extract for constant index.
 
-Improve vec_extract of V4SF from memory with constant element.
+This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
+where the element number is constant combined with a conversion to DFmode.
+
+2023-04-14   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.
+
+==================== Branch work118, patch #61 ====================
+
+Allow vec_extract support functions to be called before reload.
 
 2023-04-14   Michael Meissner  <meissner@linux.ibm.com>
 
@@ -66,11 +71,8 @@ gcc/
 	register allocation.
 	(adjust_vec_address_pcrel): Likewise.
 	(rs6000_adjust_vec_address): Likewise.
-	* config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before
-	register allocation.
-	(vsx_extract_v4sf_to_df_load): New insn.
 
-==================== Branch work118, patch #50 ====================
+==================== Branch work118, patch #60 ====================
 
 Fix typo in insn name.
 
@@ -87,6 +89,18 @@ gcc/
 	* config/rs6000/vsx.md (vsx_extract_v4sf_load): Rename from
 	vsx_extract_v4sf_<mode>_load.
 
+==================== Branch work118, patch #55 was reverted ====================
+
+==================== Branch work118, patch #54 was reverted ====================
+
+==================== Branch work118, patch #53 was reverted ====================
+
+==================== Branch work118, patch #52 was reverted ====================
+
+==================== Branch work118, patch #51 was reverted ====================
+
+==================== Branch work118, patch #50 was reveted ====================
+
 ==================== Branch work118, patch #42 was reverted ====================
 
 ==================== Branch work118, patch #41 was reverted ====================

[gcc(refs/users/meissner/heads/work118)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:253bdd0d8b957d0b392a3991083ad4fe2c51e147

commit 253bdd0d8b957d0b392a3991083ad4fe2c51e147
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 14 13:19:28 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 71bb4d6e9d9..2cd1d02b800 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,16 @@
+==================== Branch work118, patch #55 ====================
+
+Add sign/zero extension to vec_extract with variable element number.
+
+2023-04-14   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (VSX_EXTRACT_SIGN): New iterator.
+	(vsx_extract_<mode>_var_load): Update length.
+	(vsx_extract_<mode>_var_load_to_sdi): New insn.
+	(vsx_extract_<mode>_var_load_to_udi): New insn.
+
 ==================== Branch work118, patch #54 ====================
 
 Add conversions fro V4SI vec_extract

[gcc(refs/users/meissner/heads/work118)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:d6e09c857baf35c0779e75fe7632f813217415d7

commit d6e09c857baf35c0779e75fe7632f813217415d7
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Apr 13 00:16:21 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 85 +++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 84 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index a201440ada3..069712f47dc 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,84 @@
+==================== Branch work118, patch #1 ====================
+
+PR 93230: Fold sign/zero extension into vec_extract.
+
+gcc/
+
+2023-04-12  Michael Meissner  <meissner@linux.ibm.com>
+
+	PR target/93230
+	* config/rs6000/rs6000.c (rs6000_split_vec_extract_var): Remove
+	support for handling MEM, users call rs6000_adjust_vec_address
+	directly.
+	* config/rs6000/vsx.md (VSX_EX_FL): New mode attribute.
+	(vsx_extract_v4sf_<mode>_load): Rename to vsx_extract_v4sf_load.
+	(vsx_extract_v4sf_to_df_load): New insn to combine vec_extract of
+	SFmode from memory being converted to DFmode.
+	(vsx_extract_v4si_<su><mode>_load): New insn to support V4SI
+	vec_extract from memory being converted to DImode directly without
+	an extra sign/zero extension.
+	(vsx_extract_v8hi_<su><mode>_load): New insn to support V8HI
+	vec_extract from memory being converted to DImode directly without
+	an extra sign/zero extension.
+	(vsx_extract_v16qi_u<mode>_load): New insn to support V16QI
+	vec_extract from memory being converted to DImode directly without
+	an extra zero extension.
+	(vsx_extract_v4si_var_load): Split V4SI extract from other small
+	integers, and add support for loading up vector registers with
+	sign/zero extension directly.
+	(vsx_extract_<mode>_var_load, VSX_EXTRACT_I2 iterator): Split
+	V8HI/V16QI vector extract from memory to handle loading vector
+	registers in addition to GPR registers.
+	(vsx_extract_<mode>_uns_di_var): New insn to optimize extracting a
+	small integer from a vector in a register and zero extending it to
+	DImode.
+	(vsx_extract_v4si_<su><mode>_var_load): New insns to support
+	combining a V4SI variable vector extract from memory with sign or
+	zero extension.
+	(vsx_extract_v8hi_<su><mode>_var_load): New insns to support
+	combining a V8HI variable vector extract from memory with sign or
+	zero extension.
+	(vsx_extract_v4si_u<mode>_var_load): New insns to support
+	combining a V16QI variable vector extract from memory with zero
+	extension.
+	(vsx_ext_v4si_fl_<mode>_load): New insn to support a V4SI vector
+	extract that is converted to floating point to avoid doing a
+	direct move.
+	(vsx_ext_v4si_ufl_<mode>_load):  New insn to support an unsigned
+	V4SI vector extract that is converted to floating point to avoid
+	doing a direct move.
+	(vsx_ext_v4si_fl_<mode>_var_load): New insn to support a V4SI
+	variable vector extract that is converted to floating point to
+	avoid doing a direct move.
+	(vsx_ext_v4si_ufl_<mode>_var_load): New insn to support an
+	unsigned V4SI variable vector extract that is converted to
+	floating point to avoid doing a direct move.
+	(vsx_ext_<VSX_EXTRACT_I2:mode>_fl_<FL_CONV:mode>_load): New insns
+	to support a V8HI/V16QI vector extract that is converted to
+	floating point to avoid doing a direct move.
+	(vsx_ext_<VSX_EXTRACT_I2:mode>_ufl_<FL_CONV:mode>_load): New insns
+	to support an unsigned V8HI/V16QI vector extract that is converted
+	to floating point to avoid doing a direct move.
+	(vsx_ext_<VSX_EXTRACT_I2:mode>_fl_<FL_CONV:mode>_vl): New insns to
+	support a variable V8HI/V16QI vector extract that is converted to
+	floating point to avoid doing a direct move.
+	(vsx_ext_<VSX_EXTRACT_I2:mode>_ufl_<FL_CONV:mode>_vl): New insns
+	to support an unsigned variable V8HI/V16QI vector extract that is
+	converted to floating point to avoid doing a direct move.
+
+gcc/testsuite/
+
+2023-04-12  Michael Meissner  <meissner@linux.ibm.com>
+
+	PR target/93230
+	* gcc.target/powerpc/fold-vec-extract-char.p8.c: Adjust
+	instruction counts.
+	* gcc.target/powerpc/fold-vec-extract-int.p8.c: Adjust
+	instruction counts.
+	* gcc.target/powerpc/fold-vec-extract-short.p8.c: Adjust
+	instruction counts.
+	* gcc.target/powerpc/pcrel-opt-inc-di.c: Fix typo.
+
 ==================== Branch work118, patch #21 ====================
 
 Improve 64->128 bit zero extension on PowerPC
@@ -18,7 +99,7 @@ gcc/testsuite/
 
 Fix splat of extract for long long and double.
 
-2023-04-11   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-12   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
@@ -30,6 +111,8 @@ gcc/testsuite/
 
 	PR target/108958
 	* gcc.target/powerpc/pr99293.c: New test.
+	* gcc.target/powerpc/builtins-1.c: Update insn count.
+
 
 ==================== Branch work118, patch #1 ====================

[gcc(refs/users/meissner/heads/work118)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:77347c83febc53c5e412789ae4c6d52a35f2c341

commit 77347c83febc53c5e412789ae4c6d52a35f2c341
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 12 12:25:13 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 8267023d894..a201440ada3 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,4 @@
-==================== Branch work118-dmf, patch #21 ====================
+==================== Branch work118, patch #21 ====================
 
 Improve 64->128 bit zero extension on PowerPC

[gcc(refs/users/meissner/heads/work118)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:557777a54ab9dcbf4ce26ba68f4373d63ace8832

commit 557777a54ab9dcbf4ce26ba68f4373d63ace8832
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 12 12:21:47 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index d9689c3cc56..8267023d894 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,20 @@
-==================== Branch work118, patch #1 ====================
+==================== Branch work118-dmf, patch #21 ====================
+
+Improve 64->128 bit zero extension on PowerPC
+
+2023-04-12   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/108958
+	* gcc/config/rs6000.md (zero_extendditi2): New insn.
+
+gcc/testsuite/
+
+	PR target/108958
+	* gcc.target/powerpc/zero-extend-di-ti.c: New test.
+
+==================== Branch work118, patch #20 ====================
 
 Fix splat of extract for long long and double.

[gcc(refs/users/meissner/heads/work118)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:7c7076c5ca1e35603a515ebf3525aeffa14ad715

commit 7c7076c5ca1e35603a515ebf3525aeffa14ad715
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Apr 11 19:24:16 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 41624a69f42..d9689c3cc56 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,22 @@
 ==================== Branch work118, patch #1 ====================
 
+Fix splat of extract for long long and double.
+
+2023-04-11   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/99293
+	* gcc/config/rs6000/vsx.md (vsx_splat_extract_<mode>): New combiner
+	insn.
+
+gcc/testsuite/
+
+	PR target/108958
+	* gcc.target/powerpc/pr99293.c: New test.
+
+==================== Branch work118, patch #1 ====================
+
 Make load/cmp fusion know about prefixed loads.
 
 The issue with the bug is the power10 load GPR + cmpi -1/0/1 fusion

[gcc(refs/users/meissner/heads/work118)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:7893614182a24ede59cce7062a68ea1530b6b85f

commit 7893614182a24ede59cce7062a68ea1530b6b85f
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Apr 11 18:57:57 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 1b3e5afac2a..41624a69f42 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,42 @@
+==================== Branch work118, patch #1 ====================
+
+Make load/cmp fusion know about prefixed loads.
+
+The issue with the bug is the power10 load GPR + cmpi -1/0/1 fusion
+optimization generates illegal assembler code.
+
+Ultimately the code was dying because the fusion load + compare -1/0/1 patterns
+did not handle the possibility that the load might be prefixed.
+
+The main cause is the prefixed attribute did not consider that fused_load_cmpi
+insns are essentially load instructions, and to check whether the load is
+prefixed.
+
+This code ensures that the prefixed attribute is correctly set for the fusion
+load plus compare immediate insns combined instruction.  This means it will
+split the insn before final is called, and the load instruction will use a
+prefixed load.
+
+The original patch by Aaron reworked the insns generated by genfusion.pl so
+that they had constraints that limited the load to be YZ, which are constraints
+that restrict the load to offsets that the non-prefixed LWA instruction can
+handle.  I will submit that patch as a second patch.  However, just setting the
+prefixed attribute correctly will correctly split the insns.
+
+2023-03-23   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/105325
+	* gcc/config/rs6000/rs6000.md (prefixed attribute): Add fused_load_cmpi
+	instructions to the list of instructions that might have a prefixed load
+	instruction.
+
+gcc/testsuite/
+
+	PR target/105325
+	* g++.target/powerpc/pr105325.C: New test.
+
 ==================== Branch work118, baseline ====================
 
 2023-04-11   Michael Meissner  <meissner@linux.ibm.com>