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* [gcc(refs/users/meissner/heads/work118)] Add sign/zero extension to vec_extract with variable element number.
@ 2023-04-14 17:18 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2023-04-14 17:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:af03659dcfeb7ec4cb84754092d4bb8f3485a7ae
commit af03659dcfeb7ec4cb84754092d4bb8f3485a7ae
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 14 13:18:19 2023 -0400
Add sign/zero extension to vec_extract with variable element number.
2023-04-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (VSX_EXTRACT_SIGN): New iterator.
(vsx_extract_<mode>_var_load): Update length.
(vsx_extract_<mode>_var_load_to_sdi): New insn.
(vsx_extract_<mode>_var_load_to_udi): New insn.
Diff:
---
gcc/config/rs6000/vsx.md | 51 ++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 49 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index e5299827118..04ba79c2542 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -233,6 +233,9 @@
|| (FLOAT128_IEEE_P (TFmode)
&& TARGET_FLOAT128_HW)")])
+;; Vector modes that we can extract with sign extension to GPR registers
+(define_mode_iterator VSX_EXTRACT_SIGN [V4SI V8HI])
+
;; Mode iterator for binary floating types that have a direct conversion
;; from 64-bit integer to floating point
(define_mode_iterator FL_CONV [SF
@@ -4097,7 +4100,8 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V16QI/V8HI/V4SI extract from memory
+;; V16QI/V8HI/V4SI extract from memory with a variable element number.
+;; The length includes the possible shift and add of the offset.
(define_insn_and_split "*vsx_extract_<mode>_var_load"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
@@ -4113,7 +4117,50 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load")
+ (set_attr "length" "12")])
+
+;; V8HI/V4SI extract from memory with sign extension
+(define_insn_and_split "*vsx_extract_<mode>_var_load_to_sdi"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (sign_extend:DI
+ (unspec:<VEC_base>
+ [(match_operand:VSX_EXTRACT_SIGN 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (sign_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "12")])
+
+;; V16QI/V8HI/V4SI extract from memory with zero extension
+(define_insn_and_split "*vsx_extract_<mode>_var_load_to_udi"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (zero_extend:DI
+ (unspec:<VEC_base>
+ [(match_operand:VSX_EXTRACT_SIGN 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "12")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/work118)] Add sign/zero extension to vec_extract with variable element number.
@ 2023-04-14 19:12 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2023-04-14 19:12 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:89bcaff7366ac14e39600ad1dd06075eafc5826a
commit 89bcaff7366ac14e39600ad1dd06075eafc5826a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 14 15:12:28 2023 -0400
Add sign/zero extension to vec_extract with variable element number.
2023-04-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (VSX_EXTRACT_SIGN): New iterator.
(vsx_extract_<mode>_var_load): Update length.
(vsx_extract_<mode>_var_load_to_sdi): New insn.
(vsx_extract_<mode>_var_load_to_udi): New insn.
Diff:
---
gcc/config/rs6000/vsx.md | 52 ++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 50 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index e5299827118..7c9e145cef9 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -233,6 +233,9 @@
|| (FLOAT128_IEEE_P (TFmode)
&& TARGET_FLOAT128_HW)")])
+;; Vector modes that we can extract with sign extension to GPR registers
+(define_mode_iterator VSX_EXTRACT_SIGN [V4SI V8HI])
+
;; Mode iterator for binary floating types that have a direct conversion
;; from 64-bit integer to floating point
(define_mode_iterator FL_CONV [SF
@@ -4097,7 +4100,9 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V16QI/V8HI/V4SI extract from memory
+;; V16QI/V8HI/V4SI extract from memory with a variable element number. The
+;; length includes the AND to keep the element number in bounds and shifting
+;; the value for indexing by HI/SI elements.
(define_insn_and_split "*vsx_extract_<mode>_var_load"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
@@ -4113,7 +4118,50 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load")
+ (set_attr "length" "12")])
+
+;; V8HI/V4SI extract from memory with sign extension
+(define_insn_and_split "*vsx_extract_<mode>_var_load_to_sdi"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (sign_extend:DI
+ (unspec:<VEC_base>
+ [(match_operand:VSX_EXTRACT_SIGN 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (sign_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "12")])
+
+;; V16QI/V8HI/V4SI extract from memory with zero extension
+(define_insn_and_split "*vsx_extract_<mode>_var_load_to_udi"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (zero_extend:DI
+ (unspec:<VEC_base>
+ [(match_operand:VSX_EXTRACT_SIGN 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "12")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-04-14 19:12 Michael Meissner
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