[gcc(refs/users/meissner/heads/work118)] Revert patches #51

[gcc(refs/users/meissner/heads/work118)] Revert patches #51

[Michael Meissner]

https://gcc.gnu.org/g:3591c3b90dc37acb10e38c73537b2346bdda3c5a

commit 3591c3b90dc37acb10e38c73537b2346bdda3c5a
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 14 14:46:40 2023 -0400

    Revert patches #51

Diff:
---
 gcc/config/rs6000/rs6000.cc | 49 +++++++++++++--------------------------------
 gcc/config/rs6000/vsx.md    | 24 +---------------------
 2 files changed, 15 insertions(+), 58 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 21d4e2caf20..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,9 +7686,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
   if (CONST_INT_P (element))
     return GEN_INT (INTVAL (element) * scalar_size);
 
-  if (GET_CODE (base_tmp) == SCRATCH)
-    base_tmp = gen_reg_rtx (Pmode);
-
   /* All insns should use the 'Q' constraint (address is a single register) if
      the element number is not a constant.  */
   gcc_assert (satisfies_constraint_Q (mem));
@@ -7707,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
   if (shift > 0)
     {
       rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
-      if (can_create_pseudo_p ())
-	base_tmp = gen_reg_rtx (Pmode);
-
       emit_insn (gen_rtx_SET (base_tmp, shift_op));
     }
 
@@ -7753,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
 
       else
 	{
-	  if (GET_CODE (base_tmp) == SCRATCH)
-	    base_tmp = gen_reg_rtx (Pmode);
-
 	  emit_move_insn (base_tmp, addr);
 	  new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
 	}
@@ -7778,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
    temporary (BASE_TMP) to fixup the address.  Return the new memory address
    that is valid for reads or writes to a given register (SCALAR_REG).
 
-   The temporary BASE_TMP might be set multiple times with this code if this is
-   called after register allocation.  */
+   This function is expected to be called after reload is completed when we are
+   splitting insns.  The temporary BASE_TMP might be set multiple times with
+   this code.  */
 
 rtx
 rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7792,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
   rtx addr = XEXP (mem, 0);
   rtx new_addr;
 
-  if (GET_CODE (base_tmp) != SCRATCH)
-    {
-      gcc_assert (!reg_mentioned_p (base_tmp, addr));
-      gcc_assert (!reg_mentioned_p (base_tmp, element));
-    }
+  gcc_assert (!reg_mentioned_p (base_tmp, addr));
+  gcc_assert (!reg_mentioned_p (base_tmp, element));
 
   /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY.  */
   gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7852,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
 	     offset, it has the benefit that if D-FORM instructions are
 	     allowed, the offset is part of the memory access to the vector
 	     element. */
-	  if (GET_CODE (base_tmp) == SCRATCH)
-	    base_tmp = gen_reg_rtx (Pmode);
-
 	  emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
 	  new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
 	}
@@ -7862,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
 
   else
     {
-      if (GET_CODE (base_tmp) == SCRATCH)
-	base_tmp = gen_reg_rtx (Pmode);
-
       emit_move_insn (base_tmp, addr);
       new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
     }
 
-    /* If register allocation has been done and the address isn't valid, move
-       the address into the temporary base register.  Some reasons it could not
-       be valid include:
+    /* If the address isn't valid, move the address into the temporary base
+       register.  Some reasons it could not be valid include:
 
        The address offset overflowed the 16 or 34 bit offset size;
        We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
        We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
        Only X_FORM loads can be done, and the address is D_FORM.  */
 
-  if (!can_create_pseudo_p ())
-    {
-      enum insn_form iform
-	= address_to_insn_form (new_addr, scalar_mode,
-				reg_to_non_prefixed (scalar_reg, scalar_mode));
+  enum insn_form iform
+    = address_to_insn_form (new_addr, scalar_mode,
+			    reg_to_non_prefixed (scalar_reg, scalar_mode));
 
-      if (iform == INSN_FORM_BAD)
-	{
-	  emit_move_insn (base_tmp, new_addr);
-	  new_addr = base_tmp;
-	}
+  if (iform == INSN_FORM_BAD)
+    {
+      emit_move_insn (base_tmp, new_addr);
+      new_addr = base_tmp;
     }
 
   return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 00f85caed62..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,7 +3549,6 @@
   [(set_attr "length" "8")
    (set_attr "type" "fp")])
 
-;; V4SF extract from memory with constant element number
 (define_insn_and_split "*vsx_extract_v4sf_load"
   [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
 	(vec_select:SF
@@ -3558,7 +3557,7 @@
    (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
   "VECTOR_MEM_VSX_P (V4SFmode)"
   "#"
-  "&& 1"
+  "&& reload_completed"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3568,27 +3567,6 @@
    (set_attr "length" "8")
    (set_attr "isa" "*,p7v,p9v,*")])
 
-;; V4SF extract from memory and convert to DFmode with constant element number
-(define_insn_and_split "*vsx_extract_v4sf_to_df_load"
-  [(set (match_operand:DF 0 "register_operand" "=f,v")
-	(float_extend:DF
-	 (vec_select:SF
-	  (match_operand:V4SF 1 "memory_operand" "m,m")
-	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
-   (clobber (match_scratch:P 3 "=&b,&b"))]
-  "VECTOR_MEM_VSX_P (V4SFmode)"
-  "#"
-  "&& 1"
-  [(set (match_dup 0)
-	(float_extend:DF (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
-					   operands[3], SFmode);
-}
-  [(set_attr "type" "fpload")
-   (set_attr "length" "8")
-   (set_attr "isa" "*,p8v")])
-
 ;; Variable V4SF extract from a register
 (define_insn_and_split "vsx_extract_v4sf_var"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")