public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc(refs/users/meissner/heads/work118)] Add conversions fro V4SI vec_extract
@ 2023-04-14 19:05 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2023-04-14 19:05 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9758dbbb898934e6714ef9b8958412c0587f93f0
commit 9758dbbb898934e6714ef9b8958412c0587f93f0
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 14 15:05:21 2023 -0400
Add conversions fro V4SI vec_extract
This patch adds combiner insns to fold in sign and zero extension of vec_extract
of V4SI with a constant element when expanding to DImode. It also adds in
combiner insns to create SFmdoe and DFmode.
2023-04-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
(vsx_extract_v4si_load_to_<mode>): New insn.
(vsx_extract_v4si_load_to_uns<mode>): New insn.
Diff:
---
gcc/config/rs6000/vsx.md | 69 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a145ae6ca3e..e5299827118 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3989,6 +3989,75 @@
[(set_attr "type" "load,load,fpload,fpload")
(set_attr "length" "4,8,4,8")])
+;; Extract a V4SI element from memory with constant element number and convert
+;; it to DImode with zero or sign extension.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,wa,wa")
+ (any_extend:DI
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "YZ,m,Z,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")]))))
+ (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], SImode);
+}
+ [(set_attr "type" "load,load,fpload,fpload")
+ (set_attr "length" "4,8,4,8")])
+
+;; Extract a V4SI element from memory with constant element number and convert
+;; it to SFmode or DFmode using signed conversion
+(define_insn_and_split "*vsx_extract_v4si_load_to_<mode>"
+ [(set (match_operand:SFDF 0 "register_operand" "=wa")
+ (float:SFDF
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
+ (clobber (match_scratch:DI 3 "=&b"))
+ (clobber (match_scratch:DI 4 "=wa"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 4)
+ (sign_extend:DI (match_dup 5)))
+ (set (match_dup 0)
+ (float:SFDF (match_dup 4)))]
+{
+ operands[5] = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
+ operands[3], SImode);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "12")])
+
+;; Extract a V4SI element from memory with constant element number and convert
+;; it to SFmode or DFmode using unsigned conversion
+(define_insn_and_split "*vsx_extract_v4si_load_to_uns<mode>"
+ [(set (match_operand:SFDF 0 "register_operand" "=wa")
+ (unsigned_float:SFDF
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
+ (clobber (match_scratch:DI 3 "=&b"))
+ (clobber (match_scratch:DI 4 "=wa"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 4)
+ (zero_extend:DI (match_dup 5)))
+ (set (match_dup 0)
+ (unsigned_float:SFDF (match_dup 4)))]
+{
+ operands[5] = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
+ operands[3], SImode);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "12")])
+
;; Extract a V8HI/V16QI element from memory with constant element number.
(define_insn_and_split "*vsx_extract_<mode>_load"
[(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/work118)] Add conversions fro V4SI vec_extract
@ 2023-04-14 16:41 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2023-04-14 16:41 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:4867a1ffb5fcaaf3c5c7fcc9ce27c965b056df0c
commit 4867a1ffb5fcaaf3c5c7fcc9ce27c965b056df0c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 14 12:40:47 2023 -0400
Add conversions fro V4SI vec_extract
This patch adds combiner insns to fold in sign and zero extension of vec_extract
of V4SI with a constant element when expanding to DImode. It also adds in
combiner insns to create SFmdoe and DFmode.
2023-04-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
(vsx_extract_v4si_load_to_<mode>): New insn.
(vsx_extract_v4si_load_to_uns<mode>): New insn.
Diff:
---
gcc/config/rs6000/vsx.md | 69 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a145ae6ca3e..e5299827118 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3989,6 +3989,75 @@
[(set_attr "type" "load,load,fpload,fpload")
(set_attr "length" "4,8,4,8")])
+;; Extract a V4SI element from memory with constant element number and convert
+;; it to DImode with zero or sign extension.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,wa,wa")
+ (any_extend:DI
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "YZ,m,Z,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")]))))
+ (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], SImode);
+}
+ [(set_attr "type" "load,load,fpload,fpload")
+ (set_attr "length" "4,8,4,8")])
+
+;; Extract a V4SI element from memory with constant element number and convert
+;; it to SFmode or DFmode using signed conversion
+(define_insn_and_split "*vsx_extract_v4si_load_to_<mode>"
+ [(set (match_operand:SFDF 0 "register_operand" "=wa")
+ (float:SFDF
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
+ (clobber (match_scratch:DI 3 "=&b"))
+ (clobber (match_scratch:DI 4 "=wa"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 4)
+ (sign_extend:DI (match_dup 5)))
+ (set (match_dup 0)
+ (float:SFDF (match_dup 4)))]
+{
+ operands[5] = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
+ operands[3], SImode);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "12")])
+
+;; Extract a V4SI element from memory with constant element number and convert
+;; it to SFmode or DFmode using unsigned conversion
+(define_insn_and_split "*vsx_extract_v4si_load_to_uns<mode>"
+ [(set (match_operand:SFDF 0 "register_operand" "=wa")
+ (unsigned_float:SFDF
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
+ (clobber (match_scratch:DI 3 "=&b"))
+ (clobber (match_scratch:DI 4 "=wa"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 4)
+ (zero_extend:DI (match_dup 5)))
+ (set (match_dup 0)
+ (unsigned_float:SFDF (match_dup 4)))]
+{
+ operands[5] = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
+ operands[3], SImode);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "12")])
+
;; Extract a V8HI/V16QI element from memory with constant element number.
(define_insn_and_split "*vsx_extract_<mode>_load"
[(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2023-04-14 19:05 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-14 19:05 [gcc(refs/users/meissner/heads/work118)] Add conversions fro V4SI vec_extract Michael Meissner
-- strict thread matches above, loose matches on Subject: below --
2023-04-14 16:41 Michael Meissner
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).