[gcc(refs/users/meissner/heads/work118)] Add float/double conversions fro V4SI vec_extract

[gcc(refs/users/meissner/heads/work118)] Add float/double conversions fro V4SI vec_extract

[Michael Meissner]

https://gcc.gnu.org/g:ccb7655efebd8f19f1104c8f9518339fd33c244b

commit ccb7655efebd8f19f1104c8f9518339fd33c244b
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 14 22:34:59 2023 -0400

    Add float/double conversions fro V4SI vec_extract
    
    This patch adds combiner insns to fold in conversion to float or double (both
    signed and unsigned) of V4SI vec_extract with a constant element.  With this
    patch, GCC will load the SImode value directly into the vector register with
    LFIWZX or LFIWAX instead of doing a LWZ and then moving the value over with a
    direct move before the floating point conversion.
    
    2023-04-14   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000.md (SIGN_ZERO): New code attribute.
            * config/rs6000/vsx.md (vsx_extract_v4si_load_to_<mode>): New insn.

Diff:
---
 gcc/config/rs6000/rs6000.md |  3 +++
 gcc/config/rs6000/vsx.md    | 25 +++++++++++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7d6c94aee5b..4868c4f1504 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -664,6 +664,9 @@
 		       (float		"")
 		       (unsigned_float	"uns")])
 
+(define_code_attr SIGN_ZERO [(float          "SIGN")
+			     (unsigned_float "ZERO")])
+
 ; Various instructions that come in SI and DI forms.
 ; A generic w/d attribute, for things like cmpw/cmpd.
 (define_mode_attr wd [(QI    "b")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 01b43310f05..5b95c900d10 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4010,6 +4010,31 @@
   [(set_attr "type" "load,load,fpload,fpload")
    (set_attr "length" "4,8,4,8")])
 
+;; Extract a V4SI element from memory with constant element number and convert
+;; it to SFmode or DFmode using signed conversion
+(define_insn_and_split "*vsx_extract_v4si_load_to_<mode>"
+  [(set (match_operand:SFDF 0 "register_operand" "=wa")
+	(any_float:SFDF
+	 (vec_select:SI
+	  (match_operand:V4SI 1 "memory_operand" "m")
+	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
+   (clobber (match_scratch:DI 3 "=&b"))
+   (clobber (match_scratch:DI 4 "=wa"))]
+  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 4)
+	(match_dup 5))
+   (set (match_dup 0)
+	(any_float:SFDF (match_dup 4)))]
+{
+  rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
+					   operands[3], SImode);
+  operands[5] = gen_rtx_<SIGN_ZERO>_EXTEND (DImode, new_mem);
+}
+  [(set_attr "type" "fpload")
+   (set_attr "length" "12")])
+
 ;; Extract a V8HI/V16QI element from memory with constant element number.
 (define_insn_and_split "*vsx_extract_<mode>_load"
   [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")