[gcc(refs/users/meissner/heads/work118)] Revert patches 67-68

[gcc(refs/users/meissner/heads/work118)] Revert patches 67-68

[Michael Meissner]

https://gcc.gnu.org/g:1b837d76c90d214ad8ae0f34a8c740dab51ac405

commit 1b837d76c90d214ad8ae0f34a8c740dab51ac405
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 14 23:17:21 2023 -0400

    Revert patches 67-68

Diff:
---
 gcc/config/rs6000/vsx.md | 54 ++----------------------------------------------
 1 file changed, 2 insertions(+), 52 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 034c781d320..5b95c900d10 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -233,9 +233,6 @@
 					   || (FLOAT128_IEEE_P (TFmode)
 					       && TARGET_FLOAT128_HW)")])
 
-;; Vector modes that we can extract with sign extension to GPR registers
-(define_mode_iterator VSX_EXTRACT_SIGN [V4SI V8HI])
-
 ;; Mode iterator for binary floating types that have a direct conversion
 ;; from 64-bit integer to floating point
 (define_mode_iterator FL_CONV [SF
@@ -4077,9 +4074,7 @@
 }
   [(set_attr "isa" "p9v,*")])
 
-;; V16QI/V8HI/V4SI extract from memory with a variable element number.  The
-;; length includes the AND to keep the element number in bounds and shifting
-;; the value for indexing by HI/SI elements.
+;; Variable V16QI/V8HI/V4SI extract from memory
 (define_insn_and_split "*vsx_extract_<mode>_var_load"
   [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
 	(unspec:<VEC_base>
@@ -4095,52 +4090,7 @@
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], <VEC_base>mode);
 }
-  [(set_attr "type" "load")
-   (set_attr "length" "12")])
-
-;; V16QI/V8HI/V4SI extract from memory with zero extension
-(define_insn_and_split "*vsx_extract_<mode>_var_load_to_udi"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,v")
-	(zero_extend:DI
-	 (unspec:<VEC_base>
-	  [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
-	   (match_operand:DI 2 "gpc_reg_operand" "r,r")]
-	 UNSPEC_VSX_EXTRACT)))
-   (clobber (match_scratch:DI 3 "=&b,&b"))]
-  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:DI (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
-					   operands[3], <VEC_base>mode);
-}
-  [(set_attr "type" "load,fpload")
-   (set_attr "length" "12")
-   (set_attr "isa" "*,p9v")])
-
-;; V8HI/V4SI extract from memory with sign extension
-(define_insn_and_split "*vsx_extract_<mode>_var_load_to_sdi"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,v")
-	(sign_extend:DI
-	 (unspec:<VEC_base>
-	  [(match_operand:VSX_EXTRACT_SIGN 1 "memory_operand" "Q,Q")
-	   (match_operand:DI 2 "gpc_reg_operand" "r,r")]
-	 UNSPEC_VSX_EXTRACT)))
-   (clobber (match_scratch:DI 3 "=&b,&b"))]
-  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& reload_completed"
-  [(set (match_dup 0)
-	(sign_extend:DI (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
-					   operands[3], <VEC_base>mode);
-}
-  [(set_attr "type" "load,fpload")
-   (set_attr "length" "12,16")
-   (set_attr "isa" "*,p9v")])
+  [(set_attr "type" "load")])
 
 ;; ISA 3.1 extract
 (define_expand "vextractl<mode>"