[gcc(refs/users/meissner/heads/work119)] Add sign/zero conversions fro V4SI vec_extract

[gcc(refs/users/meissner/heads/work119)] Add sign/zero conversions fro V4SI vec_extract

[Michael Meissner]

https://gcc.gnu.org/g:577ade1c244e73596489a6e7ba9a0f13f7dd16b6

commit 577ade1c244e73596489a6e7ba9a0f13f7dd16b6
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Apr 17 18:25:34 2023 -0400

    Add sign/zero conversions fro V4SI vec_extract
    
    This patch adds combiner insns to fold in sign and zero extension of vec_extract
    of V4SI with a constant element when expanding to DImode.
    
    2023-04-17   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-int-2.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 21 ++++++++++++
 .../gcc.target/powerpc/vec-extract-mem-int-2.c     | 37 ++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 26caf81b01b..1c926158eb4 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3948,6 +3948,27 @@
   [(set_attr "type" "load,load,fpload,fpload")
    (set_attr "length" "4,8,4,8")])
 
+;; Extract a V4SI element from memory with constant element number and convert
+;; it to DImode with zero or sign extension.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
+  [(set (match_operand:DI 0 "register_operand" "=r,r,wa,wa")
+	(any_extend:DI
+	 (vec_select:SI
+	  (match_operand:V4SI 1 "memory_operand" "YZ,m,Z,Q")
+	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")]))))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+	(any_extend:DI (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SImode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "4,8,4,8")])
+
 ;; Extract a V8HI/V16QI element from memory with constant element number.
 (define_insn_and_split "*vsx_extract_<mode>_load"
   [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..e5452818b0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-require-effective-target p8vector_hw } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   SImode and fold the sign/extension into the load.  */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+  return vec_extract (*p, 0);		/* lwa, no extsw.  */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+  return vec_extract (*p, 1);		/* lwa, no extsw.  */
+}
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+  return vec_extract (*p, 0);		/* lwz, no rldicl.  */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+  return vec_extract (*p, 0);		/* lwz, no rldicl.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlwa\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mlwz\M}   2 } } */
+/* { dg-final { scan-assembler-not   {\mextsw\M}   } } */
+/* { dg-final { scan-assembler-not   {\mrldicl\M}  } } */