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* [gcc(refs/users/meissner/heads/work119)] Add float/double conversions fro V4SI vec_extract
@ 2023-04-18 5:43 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2023-04-18 5:43 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:880443108f4b425a0477ff53aeaa5a91d9b45be1
commit 880443108f4b425a0477ff53aeaa5a91d9b45be1
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 18 01:43:39 2023 -0400
Add float/double conversions fro V4SI vec_extract
This patch adds combiner insns to fold in conversion to float, double, or the
IEEE 128-bit types (both signed and unsigned) of V4SI vec_extract with a
constant element. With this patch, GCC will load the SImode value directly into
the vector register with LFIWZX or LFIWAX instead of doing a LWZ and then moving
the value over with a direct move before the floating point conversion.
2023-04-18 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (SIGN_ZERO): New code attribute.
(FL_CONSTRAINT): New code attribute.
(vsx_extract_v4si_load_to_<uns><mode): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 40 ++++++++++++++++++++++
| 40 ++++++++++++++++++++++
2 files changed, 80 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 1c926158eb4..49da544bf28 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -241,6 +241,17 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
+;; Constraint to use for floating point types that a direct conversion
+;; from 64-bit integer to floating point.
+(define_mode_attr FL_CONSTRAINT [(SF "wa")
+ (DF "wa")
+ (KF "v")
+ (TF "v")])
+
+;; Whether to use SIGN or ZERO when depending on the floating point conversion.
+(define_code_attr SIGN_ZERO [(float "SIGN")
+ (unsigned_float "ZERO")])
+
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -3969,6 +3980,35 @@
[(set_attr "type" "load,load,fpload,fpload")
(set_attr "length" "4,8,4,8")])
+;; Extract a V4SI element from memory with constant element number and convert
+;; it to SFmode, DFmode, KFmode, or possibly TFmode using either signed or
+;; unsigned conversion.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
+ [(set (match_operand:FL_CONV 0 "register_operand" "=<FL_CONSTRAINT>")
+ (any_float:FL_CONV
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
+ (clobber (match_scratch:DI 3 "=&b"))
+ (clobber (match_scratch:DI 4 "=<FL_CONSTRAINT>"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 4)
+ (match_dup 5))
+ (set (match_dup 0)
+ (any_float:FL_CONV (match_dup 4)))]
+{
+ if (GET_CODE (operands[4]) == SCRATCH)
+ operands[4] = gen_reg_rtx (DImode);
+
+ rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
+ operands[3], SImode);
+ operands[5] = gen_rtx_<SIGN_ZERO>_EXTEND (DImode, new_mem);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "12")])
+
;; Extract a V8HI/V16QI element from memory with constant element number.
(define_insn_and_split "*vsx_extract_<mode>_load"
[(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
new file mode 100644
index 00000000000..edaa2ccc9bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-require-effective-target float128 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and convert the value to float, double, and _Float128 by loading the
+ value directly into a vector register, and not loading up the GPRs
+ first. */
+
+#include <altivec.h>
+
+float
+extract_float_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
+}
+
+double
+extract_double_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
+}
+
+double
+extract_double_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
+}
+
+_Float128
+extract_ieee_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lfiwzx or lxsiwzx. */
+}
+
+/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Add float/double conversions fro V4SI vec_extract
@ 2023-04-18 3:33 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2023-04-18 3:33 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ba72e1fd0db48fc19af27061dd52b9ab550a4347
commit ba72e1fd0db48fc19af27061dd52b9ab550a4347
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 17 23:32:44 2023 -0400
Add float/double conversions fro V4SI vec_extract
This patch adds combiner insns to fold in conversion to float, double, or the
IEEE 128-bit types (both signed and unsigned) of V4SI vec_extract with a
constant element. With this patch, GCC will load the SImode value directly into
the vector register with LFIWZX or LFIWAX instead of doing a LWZ and then moving
the value over with a direct move before the floating point conversion.
2023-04-17 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (SIGN_ZERO): New code attribute.
(FL_CONSTRAINT): New code attribute.
(vsx_extract_v4si_load_to_<uns><mode): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 40 ++++++++++++++++++++++
| 40 ++++++++++++++++++++++
2 files changed, 80 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 1c926158eb4..49da544bf28 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -241,6 +241,17 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
+;; Constraint to use for floating point types that a direct conversion
+;; from 64-bit integer to floating point.
+(define_mode_attr FL_CONSTRAINT [(SF "wa")
+ (DF "wa")
+ (KF "v")
+ (TF "v")])
+
+;; Whether to use SIGN or ZERO when depending on the floating point conversion.
+(define_code_attr SIGN_ZERO [(float "SIGN")
+ (unsigned_float "ZERO")])
+
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -3969,6 +3980,35 @@
[(set_attr "type" "load,load,fpload,fpload")
(set_attr "length" "4,8,4,8")])
+;; Extract a V4SI element from memory with constant element number and convert
+;; it to SFmode, DFmode, KFmode, or possibly TFmode using either signed or
+;; unsigned conversion.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
+ [(set (match_operand:FL_CONV 0 "register_operand" "=<FL_CONSTRAINT>")
+ (any_float:FL_CONV
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
+ (clobber (match_scratch:DI 3 "=&b"))
+ (clobber (match_scratch:DI 4 "=<FL_CONSTRAINT>"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 4)
+ (match_dup 5))
+ (set (match_dup 0)
+ (any_float:FL_CONV (match_dup 4)))]
+{
+ if (GET_CODE (operands[4]) == SCRATCH)
+ operands[4] = gen_reg_rtx (DImode);
+
+ rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
+ operands[3], SImode);
+ operands[5] = gen_rtx_<SIGN_ZERO>_EXTEND (DImode, new_mem);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "12")])
+
;; Extract a V8HI/V16QI element from memory with constant element number.
(define_insn_and_split "*vsx_extract_<mode>_load"
[(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
new file mode 100644
index 00000000000..5dfd94832a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-require-effective-target float128 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and convert the value to float, double, and _Float128 by loading the
+ value directly into a vector register, and not loading up the GPRs
+ first. */
+
+#include <altivec.h>
+
+float
+extract_float_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
+}
+
+double
+extract_double_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
+}
+
+double
+extract_double_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
+}
+
+_Float128
+extract_ieee_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lfiwzx or lxsiwzx. */
+}
+
+/* { dg-final { scan-assembler-times {\ml(f|xs)iwax\M} 2 } } */
+/* { dg-final { scan-assembler-times {\ml(f|xs)iwzx\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
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