[gcc r14-37] aarch64: Use standard RTL codes for __rev16 intrinsic expansion

[gcc r14-37] aarch64: Use standard RTL codes for __rev16 intrinsic expansion

[Kyrylo Tkachov]

https://gcc.gnu.org/g:18e78844e78d7096c8e073c5b431480a0b8249d0

commit r14-37-g18e78844e78d7096c8e073c5b431480a0b8249d0
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Apr 18 15:06:49 2023 +0100

    aarch64: Use standard RTL codes for __rev16 intrinsic expansion
    
    I noticed for the expansion of the __rev16* arm_acle.h intrinsics we don't need to use an unspec just because it doesn't match neatly to a bswap code.
    We have organic combine patterns for it that we can reuse.
    This patch removes the define_insn using UNSPEC_REV (should it have been an UNSPEC_REV16?) and adds an expander to emit
    the patterns we have for rev16 using standard RTL codes.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64.md (@aarch64_rev16<mode>): Change to
            define_expand.
            (rev16<mode>2): Rename to...
            (aarch64_rev16<mode>2_alt1): ... This.
            (rev16<mode>2_alt): Rename to...
            (*aarch64_rev16<mode>2_alt2): ... This.

Diff:
---
 gcc/config/aarch64/aarch64.md | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 022eef80bc1..065cf4bd8b6 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -6120,13 +6120,6 @@
   [(set_attr "type" "rev")]
 )
 
-(define_insn "@aarch64_rev16<mode>"
-  [(set (match_operand:GPI 0 "register_operand" "=r")
-	(unspec:GPI [(match_operand:GPI 1 "register_operand" "r")] UNSPEC_REV))]
-  ""
-  "rev16\\t%<w>0, %<w>1"
-  [(set_attr "type" "rev")])
-
 (define_insn "*aarch64_bfxil<mode>"
   [(set (match_operand:GPI 0 "register_operand" "=r,r")
     (ior:GPI (and:GPI (match_operand:GPI 1 "register_operand" "r,0")
@@ -6183,7 +6176,7 @@
 ;; operations within an IOR/AND RTX, therefore we have two patterns matching
 ;; each valid permutation.
 
-(define_insn "rev16<mode>2"
+(define_insn "aarch64_rev16<mode>2_alt1"
   [(set (match_operand:GPI 0 "register_operand" "=r")
         (ior:GPI (and:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r")
                                       (const_int 8))
@@ -6197,7 +6190,7 @@
   [(set_attr "type" "rev")]
 )
 
-(define_insn "rev16<mode>2_alt"
+(define_insn "*aarch64_rev16<mode>2_alt2"
   [(set (match_operand:GPI 0 "register_operand" "=r")
         (ior:GPI (and:GPI (lshiftrt:GPI (match_operand:GPI 1 "register_operand" "r")
                                         (const_int 8))
@@ -6220,6 +6213,21 @@
   [(set_attr "type" "rev")]
 )
 
+;; Expander for __rev16 intrinsics.  We have organic RTL patterns for rev16 above.
+;; Use this expander to just create the shift constants needed.
+(define_expand "@aarch64_rev16<mode>"
+  [(match_operand:GPI 0 "register_operand")
+   (match_operand:GPI 1 "register_operand")]
+  ""
+  {
+    rtx left = gen_int_mode (HOST_WIDE_INT_C (0xff00ff00ff00ff00), <MODE>mode);
+    rtx right = gen_int_mode (HOST_WIDE_INT_C (0xff00ff00ff00ff), <MODE>mode);
+    emit_insn (gen_aarch64_rev16<mode>2_alt1 (operands[0], operands[1],
+					      right, left));
+    DONE;
+  }
+)
+
 ;; -------------------------------------------------------------------
 ;; Floating-point intrinsics
 ;; -------------------------------------------------------------------