[gcc r13-7220] RISC-V: Clean up the pr106602.c testcase

[gcc r13-7220] RISC-V: Clean up the pr106602.c testcase

[Palmer Dabbelt]

https://gcc.gnu.org/g:a252c73b1f2b920d8a2ff2e8ca59989e06652fbb

commit r13-7220-ga252c73b1f2b920d8a2ff2e8ca59989e06652fbb
Author: Palmer Dabbelt <palmer@rivosinc.com>
Date:   Mon Apr 17 11:20:42 2023 -0700

    RISC-V: Clean up the pr106602.c testcase
    
    The test case that was added is rv64i-specific, as there's better ways
    to generate this code on rv32i (where the long/int cast is a NOP) and on
    rv64i_zba (where we have word shifts).  This renames the original test
    case and adds two more for those targets.
    
    gcc/testsuite/ChangeLog:
            PR target/106602
            * gcc.target/riscv/pr106602.c: Moved to...
            * gcc.target/riscv/pr106602-rv64i.c: ...here.
            * gcc.target/riscv/pr106602-rv32i.c: New test.
            * gcc.target/riscv/pr106602-rv64i_zba.c: New test.
    
    (cherry picked from commit 8c010f6fe5ebe80d2e054b31e04ae0e9f12ae368)

Diff:
---
 gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c           | 14 ++++++++++++++
 .../gcc.target/riscv/{pr106602.c => pr106602-rv64i.c}     |  2 +-
 gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c       | 15 +++++++++++++++
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c
new file mode 100644
index 00000000000..05b54db7486
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-O2 -march=rv32i -mabi=ilp32" } */
+
+unsigned long
+foo2 (unsigned long a)
+{
+  return (unsigned long)(unsigned int) a << 6;
+}
+
+/* { dg-final { scan-assembler-times "slli\t" 1 } } */
+/* { dg-final { scan-assembler-not "srli\t" } } */
+/* { dg-final { scan-assembler-not "\tli\t" } } */
+/* { dg-final { scan-assembler-not "addi\t" } } */
+/* { dg-final { scan-assembler-not "and\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/pr106602.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c
similarity index 88%
rename from gcc/testsuite/gcc.target/riscv/pr106602.c
rename to gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c
index 825b1a143b5..ef0719f4a9a 100644
--- a/gcc/testsuite/gcc.target/riscv/pr106602.c
+++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { riscv64*-*-* } } } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -march=rv64i -mabi=lp64" } */
 
 unsigned long
 foo2 (unsigned long a)
diff --git a/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c
new file mode 100644
index 00000000000..23b9f1e60f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-O2 -march=rv64i_zba -mabi=lp64" } */
+
+unsigned long
+foo2 (unsigned long a)
+{
+  return (unsigned long)(unsigned int) a << 6;
+}
+
+/* { dg-final { scan-assembler-times "slli.uw\t" 1 } } */
+/* { dg-final { scan-assembler-not "slli\t" } } */
+/* { dg-final { scan-assembler-not "srli\t" } } */
+/* { dg-final { scan-assembler-not "\tli\t" } } */
+/* { dg-final { scan-assembler-not "addi\t" } } */
+/* { dg-final { scan-assembler-not "and\t" } } */