[gcc r14-62] aarch64: PR target/108840 Simplify register shift RTX costs and eliminate shift amount masking

[gcc r14-62] aarch64: PR target/108840 Simplify register shift RTX costs and eliminate shift amount masking

[Kyrylo Tkachov]

https://gcc.gnu.org/g:136330bf637b50a4f10ace017a4316541386b9c0

commit r14-62-g136330bf637b50a4f10ace017a4316541386b9c0
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Apr 19 09:34:40 2023 +0100

    aarch64: PR target/108840 Simplify register shift RTX costs and eliminate shift amount masking
    
    In this PR we fail to eliminate explicit &31 operations for variable shifts such as in:
    void
    bar (int x[3], int y)
    {
      x[0] <<= (y & 31);
      x[1] <<= (y & 31);
      x[2] <<= (y & 31);
    }
    
    This is rejected by RTX costs that end up giving too high a cost for:
    (set (reg:SI 96)
        (ashift:SI (reg:SI 98)
            (subreg:QI (and:SI (reg:SI 99)
                    (const_int 31 [0x1f])) 0)))
    
    There is code to handle the AND-31 case in rtx costs, but it gets confused by the subreg.
    It's easy enough to fix by looking inside the subreg when costing the expression.
    While doing that I noticed that the ASHIFT case and the other shift-like cases are almost identical
    and we should just merge them. This code will only be used for valid insns anyway, so the code after this
    patch should do the Right Thing (TM) for all such shift cases.
    
    With this patch there are no more "and wn, wn, 31" instructions left in the testcase.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
            PR target/108840
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64.cc (aarch64_rtx_costs): Merge ASHIFT and
            ROTATE, ROTATERT, LSHIFTRT, ASHIFTRT cases.  Handle subregs in op1.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/aarch64/pr108840.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64.cc               | 63 +++++------------------------
 gcc/testsuite/gcc.target/aarch64/pr108840.c | 38 +++++++++++++++++
 2 files changed, 49 insertions(+), 52 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index adbdaaf8603..0d7470c05a1 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -14678,6 +14678,10 @@ cost_plus:
 	}
       return false;
 
+    case ROTATE:
+    case ROTATERT:
+    case LSHIFTRT:
+    case ASHIFTRT:
     case ASHIFT:
       op0 = XEXP (x, 0);
       op1 = XEXP (x, 1);
@@ -14693,8 +14697,8 @@ cost_plus:
 		}
 	      else
 		{
-		  /* LSL (immediate), UBMF, UBFIZ and friends.  These are all
-		     aliases.  */
+		  /* LSL (immediate), ASR (immediate), UBMF, UBFIZ and friends.
+		     These are all aliases.  */
 		  *cost += extra_cost->alu.shift;
 		}
 	    }
@@ -14718,9 +14722,13 @@ cost_plus:
 	  else
 	    {
 	      if (speed)
-		/* LSLV.  */
+		/* LSLV, ASRV.  */
 		*cost += extra_cost->alu.shift_reg;
 
+	       /* The register shift amount may be in a shorter mode expressed
+		  as a lowpart SUBREG.  For costing purposes just look inside.  */
+	      if (SUBREG_P (op1) && subreg_lowpart_p (op1))
+		op1 = SUBREG_REG (op1);
 	      if (GET_CODE (op1) == AND && REG_P (XEXP (op1, 0))
 		  && CONST_INT_P (XEXP (op1, 1))
 		  && known_eq (INTVAL (XEXP (op1, 1)),
@@ -14735,55 +14743,6 @@ cost_plus:
 	  return false;  /* All arguments need to be in registers.  */
         }
 
-    case ROTATE:
-    case ROTATERT:
-    case LSHIFTRT:
-    case ASHIFTRT:
-      op0 = XEXP (x, 0);
-      op1 = XEXP (x, 1);
-
-      if (CONST_INT_P (op1))
-	{
-	  /* ASR (immediate) and friends.  */
-	  if (speed)
-	    {
-	      if (VECTOR_MODE_P (mode))
-		*cost += extra_cost->vect.alu;
-	      else
-		*cost += extra_cost->alu.shift;
-	    }
-
-	  *cost += rtx_cost (op0, mode, (enum rtx_code) code, 0, speed);
-	  return true;
-	}
-      else
-	{
-	  if (VECTOR_MODE_P (mode))
-	    {
-	      if (speed)
-		/* Vector shift (register).  */
-		*cost += extra_cost->vect.alu;
-	    }
-	  else
-	    {
-	      if (speed)
-		/* ASR (register) and friends.  */
-		*cost += extra_cost->alu.shift_reg;
-
-	      if (GET_CODE (op1) == AND && REG_P (XEXP (op1, 0))
-		  && CONST_INT_P (XEXP (op1, 1))
-		  && known_eq (INTVAL (XEXP (op1, 1)),
-			       GET_MODE_BITSIZE (mode) - 1))
-		{
-		  *cost += rtx_cost (op0, mode, (rtx_code) code, 0, speed);
-		  /* We already demanded XEXP (op1, 0) to be REG_P, so
-		     don't recurse into it.  */
-		  return true;
-		}
-	    }
-	  return false;  /* All arguments need to be in registers.  */
-	}
-
     case SYMBOL_REF:
 
       if (aarch64_cmodel == AARCH64_CMODEL_LARGE
diff --git a/gcc/testsuite/gcc.target/aarch64/pr108840.c b/gcc/testsuite/gcc.target/aarch64/pr108840.c
new file mode 100644
index 00000000000..804c1cd9156
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr108840.c
@@ -0,0 +1,38 @@
+/* PR target/108840.  Check that the explicit &31 is eliminated.  */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+int
+foo (int x, int y)
+{
+  return x << (y & 31);
+}
+
+void
+bar (int x[3], int y)
+{
+  x[0] <<= (y & 31);
+  x[1] <<= (y & 31);
+  x[2] <<= (y & 31);
+}
+
+void
+baz (int x[3], int y)
+{
+  y &= 31;
+  x[0] <<= y;
+  x[1] <<= y;
+  x[2] <<= y;
+}
+
+void corge (int, int, int);
+
+void
+qux (int x, int y, int z, int n)
+{
+  n &= 31;
+  corge (x << n, y << n, z >> n);
+}
+
+/* { dg-final { scan-assembler-not {and\tw[0-9]+, w[0-9]+, 31} } } */
+