[gcc r14-86] RISC-V: Align IOR optimization MODE_CLASS condition to AND.

[gcc r14-86] RISC-V: Align IOR optimization MODE_CLASS condition to AND.

[Kito Cheng]

https://gcc.gnu.org/g:978e8f02e8edebaf21ce32768cce603f650459e4

commit r14-86-g978e8f02e8edebaf21ce32768cce603f650459e4
Author: Pan Li <pan2.li@intel.com>
Date:   Wed Apr 19 17:18:20 2023 +0800

    RISC-V: Align IOR optimization MODE_CLASS condition to AND.
    
    This patch aligned the MODE_CLASS condition of the IOR to the AND. Then
    more MODE_CLASS besides SCALAR_INT can able to perform the optimization
    A | (~A) -> -1 similar to AND operator. For example as below sample code.
    
    vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t vl)
    {
      return __riscv_vmorn_mm_b32(v1, v1, vl);
    }
    
    Before this patch:
    vsetvli  a5,zero,e8,mf4,ta,ma
    vlm.v    v24,0(a1)
    vsetvli  zero,a2,e8,mf4,ta,ma
    vmorn.mm v24,v24,v24
    vsetvli  a5,zero,e8,mf4,ta,ma
    vsm.v    v24,0(a0)
    ret
    
    After this patch:
    vsetvli zero,a2,e8,mf4,ta,ma
    vmset.m v24
    vsetvli a5,zero,e8,mf4,ta,ma
    vsm.v   v24,0(a0)
    ret
    
    Or in RTL's perspective,
    from:
    (ior:VNx2BI (reg/v:VNx2BI 137 [ v1 ]) (not:VNx2BI (reg/v:VNx2BI 137 [ v1 ])))
    to:
    (const_vector:VNx2BI repeat [ (const_int 1 [0x1]) ])
    
    The similar optimization like VMANDN has enabled already. There should
    be no difference execpt the operator when compare the VMORN and VMANDN
    for such kind of optimization. The patch aligns the IOR MODE_CLASS condition
    of the simplification to the AND operator.
    
    gcc/ChangeLog:
    
            * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
            Align IOR (A | (~A) -> -1) optimization MODE_CLASS condition to AND.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Update check
            condition.
            * gcc.target/riscv/simplify_ior_optimization.c: New test.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>

Diff:
---
 gcc/simplify-rtx.cc                                |  4 +-
 .../gcc.target/riscv/rvv/base/mask_insn_shortcut.c |  3 +-
 .../gcc.target/riscv/simplify_ior_optimization.c   | 50 ++++++++++++++++++++++
 3 files changed, 53 insertions(+), 4 deletions(-)

diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
index c57ff3320ee..d4aeebc7a5f 100644
--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
@@ -3370,8 +3370,8 @@ simplify_context::simplify_binary_operation_1 (rtx_code code,
       if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1))
 	   || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0)))
 	  && ! side_effects_p (op0)
-	  && SCALAR_INT_MODE_P (mode))
-	return constm1_rtx;
+	  && GET_MODE_CLASS (mode) != MODE_CC)
+	return CONSTM1_RTX (mode);
 
       /* (ior A C) is C if all bits of A that might be nonzero are on in C.  */
       if (CONST_INT_P (op1)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
index 83cc4a1b5a5..57d0241675a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
@@ -233,9 +233,8 @@ vbool64_t test_shortcut_for_riscv_vmxnor_case_6(vbool64_t v1, size_t vl) {
 /* { dg-final { scan-assembler-not {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
 /* { dg-final { scan-assembler-not {vmor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
 /* { dg-final { scan-assembler-not {vmnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
-/* { dg-final { scan-assembler-times {vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
 /* { dg-final { scan-assembler-not {vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
 /* { dg-final { scan-assembler-times {vmclr\.m\s+v[0-9]+} 14 } } */
-/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 14 } } */
 /* { dg-final { scan-assembler-times {vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 14 } } */
 /* { dg-final { scan-assembler-times {vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
new file mode 100644
index 00000000000..ec3bd0baf03
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
+
+#include <stdint.h>
+
+uint8_t test_simplify_ior_scalar_case_0 (uint8_t a)
+{
+  return a | ~a;
+}
+
+uint16_t test_simplify_ior_scalar_case_1 (uint16_t a)
+{
+  return a | ~a;
+}
+
+uint32_t test_simplify_ior_scalar_case_2 (uint32_t a)
+{
+  return a | ~a;
+}
+
+uint64_t test_simplify_ior_scalar_case_3 (uint64_t a)
+{
+  return a | ~a;
+}
+
+int8_t test_simplify_ior_scalar_case_4 (int8_t a)
+{
+  return a | ~a;
+}
+
+int16_t test_simplify_ior_scalar_case_5 (int16_t a)
+{
+  return a | ~a;
+}
+
+int32_t test_simplify_ior_scalar_case_6 (int32_t a)
+{
+  return a | ~a;
+}
+
+int64_t test_simplify_ior_scalar_case_7 (int64_t a)
+{
+  return a | ~a;
+}
+
+/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*-1} 6 } } */
+/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*255} 1 } } */
+/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*65536} 1 } } */
+/* { dg-final { scan-assembler-not {or\s+a[0-9]+} } } */
+/* { dg-final { scan-assembler-not {not\s+a[0-9]+} } } */